公开(公告)号：US20160268666A1

公开(公告)日：2016-09-15

申请号：US15159967

申请日：2016-05-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yuki WAKABAYASHI ,  Bunta OKAMOTO ,  Satoshi SASAKI

IPC: H01P3/08 ,  H05K1/02

CPC classification number: H01P3/08 ,  H01P1/2039 ,  H01P3/082 ,  H05K1/0237 ,  H05K1/028 ,  H05K1/111 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09609 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/10189

Abstract: A high-frequency signal line includes a dielectric base with a first line portion and a second line portion each extending along a predetermined straight line parallel or substantially parallel to a predetermined direction, and a third line portion mutually connecting first side ends of the first line portion and the second line portion in the predetermined direction, a signal line, a first ground conductor located on the first side in the layer stacking direction of the signal line, a second ground conductor located on a second side in the layer stacking direction of the signal line, and one or more interlayer connection conductors connecting the first ground conductor and the second ground conductor. In the third line portion, the interlayer connection conductor is provided on the second side in the predetermined direction of the signal line when viewed from the layer stacking direction.

Abstract translation: 高频信号线包括：电介质基底，具有第一线部分和第二线部分，每个第二线部分沿着与预定方向平行或基本平行的预定直线延伸;以及第三线部分，其相互连接第一线的第一侧端 部分和第二线部分，信号线，位于信号线的层叠方向的第一侧的第一接地导体，位于第二接线导体的层叠方向上的第二接地导体 信号线和连接第一接地导体和第二接地导体的一个或多个层间连接导体。 在第三行部分中，当从层叠方向观察时，层间连接导体设置在信号线的预定方向上的第二侧上。

公开(公告)号：US09443788B2

公开(公告)日：2016-09-13

申请号：US13966633

申请日：2013-08-14

Applicant: Dai Nippon Printing Co., Ltd.

Inventor： Takamasa Takano

IPC: H05K1/11 ,  H01L23/48 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498 ,  H05K3/42 ,  H05K3/44

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894 ,  H01L24/17 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/1579 ,  H05K1/113 ,  H05K3/426 ,  H05K3/445 ,  H05K2201/09436 ,  H05K2201/09581 ,  H05K2201/09609 ,  H05K2201/09836 ,  H05K2201/09854 ,  H05K2201/10378 ,  H05K2203/0733 ,  H05K2203/1178 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49165 ,  H01L2224/05647 ,  H01L2924/01024 ,  H01L2924/01079

Abstract: A method of manufacturing a through-hole electrode substrate includes forming a plurality of through-holes in a substrate, forming a plurality of through-hole electrodes by filling a conductive material into the plurality of through-holes, forming a first insulation layer on one surface of the substrate, forming a plurality of first openings which expose the plurality of through-hole electrodes corresponding to each of the plurality of through-hole electrodes, on the first insulation layer and correcting a position of the plurality of first openings using the relationship between a misalignment amount of a measured distance value of an open position of a leaning through-hole among the plurality of through-holes and of a design distance value of the open position of the leaning through-hole among the plurality of through-holes with respect to a center position of the substrate.

Abstract translation: 一种制造通孔电极基板的方法包括在基板上形成多个通孔，通过在多个通孔中填充导电材料形成多个通孔电极，在一个通孔上形成第一绝缘层 在所述第一绝缘层上形成多个第一开口，所述多个第一开口将与所述多个通孔电极中的每一个相对应的多个通孔电极暴露在所述第一绝缘层上，并且使用所述关系来校正所述多个第一开口的位置 在多个通孔中的倾斜通孔的打开位置的测量距离值的偏移量与多个通孔中的倾斜通孔的打开位置的设计距离值之间， 相对于基板的中心位置。

公开(公告)号：US20160205770A1

公开(公告)日：2016-07-14

申请号：US14593735

申请日：2015-01-09

Applicant: ORACLE INTERNATIONAL CORPORATION

Inventor： DARKO R. POPOVIC

IPC: H05K1/02 ,  H01R43/20

CPC classification number: H01R43/205 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/552 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/0228 ,  H05K1/0245 ,  H05K2201/09609 ,  H05K2201/09636

Abstract: Embodiments reduce crosstalk between electrical interconnects by offsetting pairs of electrical interconnects in an electrical system to produce a staggered interconnect pattern for which magnetic flux through a loop formed by a victim interconnect pair is effectively canceled. Magnetic field vectors generated by an aggressor pair of interconnects can pass through a loop-bounded surface defined by a victim pair of interconnects in the system. In the staggered interconnect pattern, the victim interconnect pair is offset with respect to the aggressor interconnect pair so that the field vectors passing through the victim pair's loop-bounded surface in one direction are substantially balanced by the field vectors passing through the victim pair's loop-bounded surface in the opposite direction, thereby minimizing the effect of the aggressor pair's magnetic field on the victim pair. Since crosstalk is proportional to the rate of change of the magnetic flux, reducing the magnetic flux can reduce the crosstalk.

Abstract translation: 实施例通过偏移电气系统中的电互连对来减少电互连之间的串扰，以产生交错的互连图案，通过由受害互连对形成的环路的磁通被有效地消除。 由侵略者互连对产生的磁场矢量可以通过系统中受害对互连对界定的循环界定的表面。 在交错的互连图案中，受害者互连对相对于侵略者互连对偏移，使得在一个方向上通过受害对的循环界限的场矢量基本上通过穿过受害者对的环路 - 相反方向的有界表面，从而最小化侵略者对的磁场对受害者对的影响。 由于串扰与磁通量的变化率成比例，所以减小磁通可以减少串扰。

公开(公告)号：US20160205768A1

公开(公告)日：2016-07-14

申请号：US14912677

申请日：2014-09-11

Applicant: NEC CORPORATION

Inventor： Kazuhiro KASHIWAKURA

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/40 ,  H05K1/11

CPC classification number: H05K1/0222 ,  H01P1/045 ,  H01P5/085 ,  H05K1/0213 ,  H05K1/0251 ,  H05K1/113 ,  H05K1/116 ,  H05K3/0047 ,  H05K3/40 ,  H05K2201/09063 ,  H05K2201/09609 ,  H05K2201/09809

Abstract: To provide a printed board that solves the problem of transmission characteristics deterioration, the disclosed printed board includes a substrate, a circular signal pad that is provided on the substrate, a doughnut-shaped ground pad, which sandwiches the substrate that surrounds, in a doughnut shape, the signal pad, and which surrounds the outer circumference of the substrate, and one or more recessed sections that are disposed on the substrate that surrounds, in the doughnut shape, the signal pad.

Abstract translation: 为了提供解决传输特性恶化的印刷电​​路板，公开的印刷电路板包括基板，设置在基板上的圆形信号焊盘，将环状的基板夹在环状的环形接地垫中 形状，信号垫，并且其围绕基板的外周;以及一个或多个凹陷部分，其设置在基板上，环形圈中包围信号垫。

公开(公告)号：US09374897B2

公开(公告)日：2016-06-21

申请号：US14823519

申请日：2015-08-11

Applicant: FANUC Corporation

Inventor： Makoto Bekke

IPC: H05K1/11

CPC classification number: H05K1/115 ,  H05K3/3447 ,  H05K2201/09545 ,  H05K2201/09609 ,  H05K2201/09636 ,  H05K2203/044

Abstract: A printed wiring board includes three or more than three through holes. An inner wall of the through hole is covered by conductive coating. Same size leads of an electronic component are inserted into the through holes. The through holes are soldered by dip soldering the printed wiring board in melting solder. The through holes have two or more diameters. The diameter of the through hole having more adjacent through holes is not larger than the diameter of the through hole having less adjacent through holes.

Abstract translation: 印刷电路板包括三个或三个以上的通孔。 通孔的内壁被导电涂层覆盖。 将电子部件的相同尺寸的引线插入到通孔中。 通孔通过浸焊焊接印刷线路板而熔化焊料来焊接通孔。 通孔具有两个或更多个直径。 具有更多相邻通孔的通孔的直径不大于具有较少相邻通孔的通孔的直径。

公开(公告)号：US09362603B2

公开(公告)日：2016-06-07

申请号：US13806824

申请日：2010-06-30

Applicant: Taras Kushta

Inventor： Taras Kushta

IPC: H01P1/203 ,  H01P1/20 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46

CPC classification number: H01P1/20 ,  H01P1/203 ,  H05K1/0222 ,  H05K1/0233 ,  H05K1/0251 ,  H05K3/429 ,  H05K3/4614 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/0979

Abstract: A filter of the present invention includes a plurality of via structures with a multilayer substrate. Each of the plurality of via structures includes first, second and third functional sections. One end of a signal via of the first functional section is connected to one end of a signal via of the second functional section and another end of the signal via of the second functional section is connected to two signal vias of the third functional section. Those signal vias are surrounded by a plurality of ground vias. Input and output ports of the filter are connected to another end of the signal via of each first functional section.

Abstract translation: 本发明的过滤器包括具有多层基板的多个通孔结构。 多个通孔结构中的每一个包括第一，第二和第三功能部分。 第一功能部的信号通路的一端连接到第二功能部的信号通路的一端，第二功能部的信号通路的另一端连接到第三功能部的两个信号通路。 那些信号通道被多个接地通孔包围。 滤波器的输入和输出端口连接到每个第一功能部分的信号通道的另一端。

公开(公告)号：US20160073500A1

公开(公告)日：2016-03-10

申请号：US14480430

申请日：2014-09-08

Applicant: Cisco Technology, Inc.

Inventor： Feng Wu ,  Yongchao Ji ,  Yang Tang ,  Stephen Scearce ,  Shunjia Liu ,  Shaochun Tang

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/115 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/114 ,  H05K1/181 ,  H05K3/3415 ,  H05K3/3436 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/10015 ,  H05K2201/10674

Abstract: Various implementations disclosed herein include arrangements that reduce parasitic inductance associated with a discrete decoupling capacitor by using a three-terminal capacitor and a staggered array of power supply and ground connections. In some implementations, a capacitive decoupling arrangement includes a substrate, an array of electrical vias of first and second types, and a capacitive arrangement on one side of the substrate coupled to the array of electrical vias. The array of electrical vias includes a first type of vias and a second type of vias. The capacitive arrangement is coupled between two respective vias of the first type of vias and two respective vias of the second type of vias on the first planar surface of the substrate. The capacitive arrangement includes a plurality of capacitive elements electrically arranged in parallel between the two respective vias of the first type of vias and the two respective vias of the second type of vias.

Abstract translation: 本文公开的各种实施方案包括通过使用三端电容器和电源和接地连接的交错阵列来减少与离散去耦电容器相关联的寄生电感的布置。 在一些实施方式中，电容去耦装置包括衬底，第一和第二类型的电通路的阵列，以及耦合到电气通孔阵列的衬底的一侧的电容布置。 电气通孔阵列包括第一类型的通孔和第二类型的通孔。 电容布置耦合在第一类型的通孔的两个相应的通孔和衬底的第一平面表面上的第二类型的通孔的两个相应的通孔之间。 电容性布置包括多个电容元件，它们并联布置在第一类型通孔的两个相应的通孔和第二类型通孔的两个相应的通孔之间。

公开(公告)号：US09253877B2

公开(公告)日：2016-02-02

申请号：US14633342

申请日：2015-02-27

Applicant: Shinko Electric Industries Co., Ltd.

Inventor： Takashi Sato ,  Ruofan Tang

IPC: H01L23/544 ,  H01L23/12 ,  H05K1/02 ,  H01L23/498 ,  H05K1/11

CPC classification number: H05K1/0269 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K1/115 ,  H05K3/4682 ,  H05K2201/09409 ,  H05K2201/09609 ,  H05K2201/09781 ,  H05K2201/09936 ,  H01L2924/00

Abstract: A wiring substrate includes wiring layers and insulation layers alternately stacked. Via holes are formed in the insulation layers. First via wirings are formed in the via holes to electrically connect the wiring layers to one another. Through holes extend through a lowermost one of the insulation layers in a thickness direction. The lowermost insulation layer covers a lowermost one of the wiring layers. Second via wirings are formed in the through holes to define an identification mark that is identifiable as a specific shape including a character, a symbol, or a combination thereof. A lower surface of each of the second via wirings is exposed from a lower surface of the lowermost insulation layer and is flush with a lower surface of the lowermost wiring layer.

Abstract translation: 布线基板包括交替堆叠的布线层和绝缘层。 在绝缘层中形成通孔。 首先通过布线形成通孔，以将布线层彼此电连接。 通孔在厚度方向上延伸穿过绝缘层中的最下面一个。 最下面的绝缘层覆盖最下面的一个布线层。 第二通孔布线形成在通孔中以形成可识别为包括字符，符号或其组合的特定形状的识别标记。 每个第二通孔布线的下表面从最下层绝缘层的下表面露出，并且与最下布线层的下表面齐平。

公开(公告)号：US09226388B2

公开(公告)日：2015-12-29

申请号：US13955474

申请日：2013-07-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang-Kyung Lee ,  Hee-Kyoung Lee ,  Dong-Hwan Lee ,  Kyung-Sang Lim

IPC: H05K9/00 ,  H05K1/03 ,  H05K1/11 ,  H05K1/02

CPC classification number: H05K1/0242 ,  H05K1/0219 ,  H05K1/0233 ,  H05K2201/086 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/0979

Abstract: A printed circuit board disclosed. One embodiment of the present invention provides a printed circuit board that includes: an insulation layer having multiple layers of circuit wirings formed therein; a via formed along a perimeter of the insulation layer and configured for connecting circuit wirings formed on different layers of the insulation layer, the via being formed in such a way that an inside thereof is hollow; and an electromagnetic wave absorbing part contained in the via.

Abstract translation: 公开了印刷电路板。 本发明的一个实施例提供了一种印刷电路板，其包括：绝缘层，其中形成有多层电路布线; 沿绝缘层的周边形成的通孔，其被构造用于连接形成在绝缘层的不同层上的电路布线，所述通孔以使其内部为中空的方式形成; 以及包含在通孔中的电磁波吸收部。

公开(公告)号：US09049786B2

公开(公告)日：2015-06-02

申请号：US13436005

申请日：2012-03-30

Applicant: Toshihisa Nomura ,  Kenji Suzuki ,  Kazushige Akita

Inventor： Toshihisa Nomura ,  Kenji Suzuki ,  Kazushige Akita

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/02 ,  H05K1/03 ,  H05K3/00 ,  H05K3/40 ,  G01R1/073 ,  G01R3/00

CPC classification number: H05K1/0287 ,  G01R1/07342 ,  G01R3/00 ,  H05K1/0306 ,  H05K1/115 ,  H05K3/005 ,  H05K3/4061 ,  H05K3/429 ,  H05K2201/0949 ,  H05K2201/09609 ,  H05K2201/0979 ,  Y10T156/11

Abstract: A ceramic substrate for an electronic part inspecting apparatus that can be manufactured in accordance with predetermined specifications, regardless of the number and location of pins required, relatively quickly and inexpensively is provided. In certain embodiments the ceramic substrate is configured to connect to a probe for inspecting an electronic component, and the ceramic substrate comprises a plurality of vias located in a center area of the ceramic substrate that penetrate through the ceramic substrate in its thicknesswise direction, pads located in an outer periphery that surrounds the center area where the vias are located, the pads being configured to connected to the probes, and a conductive layer located only over the front surface of the ceramic substrate and connects the vias to the respective pads. Certain embodiments comprise a greater number of vias than pins. A method of manufacturing the ceramic substrate is also provided.

Abstract translation: 提供了一种用于电子部件检查装置的陶瓷基板，其可以根据预定规格制造，而不管所需的销的数量和位置如何，相对快速且低成本地进行。 在某些实施例中，陶瓷衬底被配置为连接到用于检查电子部件的探针，并且陶瓷衬底包括位于陶瓷衬底的沿其厚度方向穿过陶瓷衬底的中心区域的多个通孔，位于 在围绕通孔所在的中心区域的外周中，衬垫被配置为连接到探针，以及导电层，其仅位于陶瓷衬底的前表面上，并将通孔连接到相应的焊盘。 某些实施例包括比引脚更多的通孔。 还提供了制造陶瓷基板的方法。