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    Layer allocating apparatus for multi-layer circuit board
    11.
    发明授权
    Layer allocating apparatus for multi-layer circuit board 有权

    公开(公告)号：US06812409B2

    公开(公告)日：2004-11-02

    申请号：US10330297

    申请日：2002-12-30

    Applicant: Chun Hung Chen ,  Hsiu Tzu Chen ,  Yen Chen Chen

    Inventor： Chun Hung Chen ,  Hsiu Tzu Chen ,  Yen Chen Chen

    IPC: H05K103

    CPC classification number: H05K1/0262 ,  H05K1/0216 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09663

    Abstract: A layer allocating apparatus for a multi-layer circuit board is disclosed. In a preferred embodiment, the layer allocating apparatus arranged from top to bottom as a component layer, a ground layer, a power layer, and a solder layer. The powerlayer is sliced into a plurality of reference ground areas each is located at somewhere to correspond to signal layout areas of the solder layer, so as to allow signal lines of the component layer and solder layer to take reference to the reference ground areas on the adjacent power layer. The power layer also includes a plurality of power layers each provides different operating voltages, and electrically couples with corresponding power layouts of the solder layer and component layer through vias, thereby enlarging the total area of power planes, so as to provide a table power source and attenuate the ground/bounce effect.

    Leadframe-based module DC bus design to reduce module inductance
    13.
    发明申请
    Leadframe-based module DC bus design to reduce module inductance 审中-公开
    基于引线框架的模块直流总线设计，减少模块电感

    公开(公告)号：US20020034088A1

    公开(公告)日：2002-03-21

    申请号：US09882708

    申请日：2001-06-15

    Inventor： Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

    IPC: H02M001/00

    CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

    Abstract: A DC bus for use in a power module has a positive DC conductor bus plate parallel with a negative DC conductor bus plate. One or more positive leads are connected to the positive bus and are connectable to a positive terminal of a power source. One or more negative leads are connected to the negative bus and are connectable to a negative terminal of a power source. The DC bus has one or more positive connections fastenable from the positive bus to the high side of a power module. The DC bus also has one or more negative connections fastenable from the negative bus to the low side of the power module. The positive bus and negative bus permit counter-flow of currents, thereby canceling magnetic fields and their associated inductances, and the positive and negative bus are connectable to the center portion of a power module.

    Abstract translation: 用于电源模块的直流母线具有与负直流导体总线板平行的正直流导体母线板。 一个或多个正极引线连接到正极母线，并且可连接到电源的正极端子。 一个或多个负极引线连接到负母线并且可连接到电源的负极端子。 DC总线具有一个或多个正极连接，可从正极母线固定到电源模块的高侧。 DC总线还具有一个或多个从负母线固定到电源模块的低端的负极连接。 正母线和负母线允许电流逆流，从而消除磁场及其相关的电感，正负母线可连接到电源模块的中心部分。

    Method and apparatus for clock uncertainty minimization with a clean power source
    15.
    发明授权
    Method and apparatus for clock uncertainty minimization with a clean power source 失效
    用于清洁电源的时钟不确定度最小化的方法和装置

    公开(公告)号：US6157250A

    公开(公告)日：2000-12-05

    申请号：US360072

    申请日：1999-07-23

    Applicant: Sergio D. Camerlo

    Inventor： Sergio D. Camerlo

    IPC: G06F1/10 ,  H05K1/02 ,  H01L25/00

    CPC classification number: H05K1/0233 ,  G06F1/10 ,  H05K1/0231 ,  H05K1/0215 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

    Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

    Abstract translation: 描述了简单地实际上没有成本，并且仅使用标准时钟驱动器和简单，便宜的电气部件来大大降低时钟数字电路中的时序不确定性的方法和装置。 该方法包括通过控制时钟偏移和时钟抖动来最小化时序不确定性的步骤。 通过将多行时钟的输出结合在布置在印刷电路板（PCB）上的电容金属岛上来消除本征时钟偏移。 通过使用匹配长度的宽的相对较高电容的迹线来控制外部时钟偏移，并且布置在PCB的单个公共信号层上，每个通向各自的接收器电路并且相同地终止。 通过电气隔离PCB的区域来控制时钟抖动，将时钟驱动器设置在该区域中以使噪声最小化，并向该区域提供安静的局部电源和接地。

    Method and apparatus for clock uncertainly minimization
    16.
    发明授权
    Method and apparatus for clock uncertainly minimization 失效
    时钟不确定性最小化的方法和装置

    公开(公告)号：US6052012A

    公开(公告)日：2000-04-18

    申请号：US106823

    申请日：1998-06-29

    Applicant: Sergio D. Camerlo

    Inventor： Sergio D. Camerlo

    IPC: G06F1/10 ,  H05K1/02 ,  G06F1/04

    CPC classification number: H05K1/0233 ,  G06F1/10 ,  H05K1/0231 ,  H05K1/0215 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

    Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

    Abstract translation: 描述了简单地实际上没有成本，并且仅使用标准时钟驱动器和简单，便宜的电气部件来大大降低时钟数字电路中的时序不确定性的方法和装置。 该方法包括通过控制时钟偏移和时钟抖动来最小化时序不确定性的步骤。 通过将多行时钟的输出结合在布置在印刷电路板（PCB）上的电容金属岛上来消除本征时钟偏移。 通过使用匹配长度的宽的相对较高电容的迹线来控制外部时钟偏移，并且布置在PCB的单个公共信号层上，每个通向相应的接收器电路并且相同地终止。 通过电气隔离PCB的区域来控制时钟抖动，将时钟驱动器设置在该区域中以使噪声最小化，并向该区域提供安静的局部电源和接地。

    Printed circuit board
    17.
    发明授权
    Printed circuit board 失效
    印刷电路板

    公开(公告)号：US5912597A

    公开(公告)日：1999-06-15

    申请号：US413908

    申请日：1995-03-30

    Applicant: Hideho Inagawa ,  Tomoyasu Arakawa ,  Toru Otaki ,  Yasushi Takeuchi ,  Yoshimi Terayama ,  Toru Osaka

    Inventor： Hideho Inagawa ,  Tomoyasu Arakawa ,  Toru Otaki ,  Yasushi Takeuchi ,  Yoshimi Terayama ,  Toru Osaka

    IPC: H05K1/00 ,  H05K1/02 ,  H03H1/00

    CPC classification number: H05K1/0216 ,  H05K1/0289 ,  H05K2201/09236 ,  H05K2201/09345 ,  H05K2201/09727 ,  H05K2201/10689

    Abstract: A printed circuit board capable of suppressing radiation noise efficiently includes a first conductive layer where a plurality of power lines are provided at predetermined spacing along one direction, a second conductive layer where a plurality of power lines are provided at predetermined spacing along a direction orthogonal to the one direction, and a plurality of plated through holes for connecting the power lines on the first conductive layer and the power lines on the second conductive layer at the overlapping points of those lines. The power lines contain thin lines and thick lines spaced between a plurality of the thin lines. The predetermined spacing is determined based on a rising time or falling time of the output signal of the IC to be mounted on the circuit board.

    Abstract translation: 能够有效地抑制辐射噪声的印刷电路板包括沿着一个方向以预定间隔设置多条电源线的第一导电层，沿着与...正交的方向以预定间隔设置多条电源线的第二导电层 一个方向，以及多个用于连接第一导电层上的电力线和第二导电层上的电力线的电镀通孔。 电力线包含在多条细线之间间隔的细线和粗线。 基于要安装在电路板上的IC的输出信号的上升时间或下降时间确定预定间隔。

    Print for control modules of contact-free control and regulating systems
    18.
    发明授权
    Print for control modules of contact-free control and regulating systems 失效
    无触点控制和调节系统控制模块的打印

    公开(公告)号：US3832602A

    公开(公告)日：1974-08-27

    申请号：US28444972

    申请日：1972-08-28

    Applicant: SIEMENS AG

    Inventor： SCHAFF U ,  KAISER W ,  ENGELHARD D ,  HOFMANN H

    IPC: H05K1/02 ,  H05K5/00

    CPC classification number: H05K1/0233 ,  H05K1/0215 ,  H05K1/0227 ,  H05K1/0231 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09345 ,  H05K2201/09663 ,  H05K2201/09972 ,  H05K2201/1006 ,  H05K2201/10166

    Abstract: A print for control modules of contact-free control and regulating systems comprising an insulating carrier plate having one portion of one surface adjacent the control inputs provided with a plurality of anti-interference filters. The number of filters is the same as the number of control inputs. The other portion of the one surface of the plate is provided with the same number of threshold value stages connected to the filters. The other surface of the carrier plate has a metal layer thereon which is electrically interrupted in accordance with the boundary between the first and second portions of the one surface thereof. The portion of the layer corresponding to the first portion is connected to ground and the portion of the layer corresponding to the second portion is connected to a reference potential.

    Abstract translation: 一种无接触式控制和调节系统的控制模块的打印件，包括绝缘载板，该绝缘载板具有与设置有多个抗干扰滤波器的控制输入相邻的一个表面的一部分。 滤波器的数量与控制输入的数量相同。 板的一个表面的另一部分设置有连接到过滤器的相同数量的阈值级。 载体板的另一个表面上具有金属层，该金属层根据其一个表面的第一和第二部分之间的边界被电中断。 对应于第一部分的层的部分连接到地面，并且对应于第二部分的层的部分连接到参考电位。

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