公开(公告)号：US20110192637A1

公开(公告)日：2011-08-11

申请号：US13089378

申请日：2011-04-19

Applicant: Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K1/03

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board includes a core structure including resin layers and conductor circuits sandwiched by the resin layers, the core structure having first and second surfaces, a first conductor layer including conductor circuits on the first surface of the core structure, and a second conductor layer including conductor circuits on the second surface of the core structure. The core structure includes first and via holes, and the first and second via holes include a metal filling up to the respective top of openings in the resin layers, respectively, sandwich one or more conductor circuits in the core structure and are positioned vertically to form a through hole electrically connecting respective ones of the conductor circuits of the first and second conductor layers, and the first and second via holes are deviated from each other in a vertical direction.

Abstract translation: 多层印刷电路板包括：包括树脂层的芯结构和被树脂层夹持的导体电路，所述芯结构具有第一和第二表面，在芯结构的第一表面上包括导体电路的第一导体层，以及 第二导体层，包括在芯结构的第二表面上的导体电路。 芯结构包括第一和通孔，并且第一和第二通孔分别包括在树脂层中分别填充到各个开口顶部的金属，将一个或多个导体电路夹在芯结构中并垂直定位以形成 电连接第一和第二导体层的各个导体电路的通孔以及第一和第二通孔在垂直方向上彼此偏离。

公开(公告)号：US20110036626A1

公开(公告)日：2011-02-17

申请号：US12913258

申请日：2010-10-27

Applicant: Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

Inventor： Motoo ASAI ,  Dongdong Wang ,  Takahiro Mori

IPC: H05K1/11

CPC classification number: H05K3/423 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/15312 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/181 ,  H05K3/381 ,  H05K3/385 ,  H05K3/387 ,  H05K3/388 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0315 ,  H05K2203/0733 ,  H05K2203/0773 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2224/05599

Abstract: A multi-layer printed circuit board including a first insulating layer, a first conductor layer having conductor circuits on one surface of the first insulating layer, a second conductor layer having conductor circuits on the opposite surface of the first insulating layer, a second insulating layer on the second conductor and first insulating layers, and a third conductor layer having conductor circuits on the second insulating layer on the opposite side of the second conductor layer. The first and second insulating layers have first and second via holes which are formed in openings of the first and second insulating layers and made of conductive materials filled to the top of the openings such that conductor circuits in the first and third conductor layers are connected to one or more conductor circuits in the second conductor layer, and the first and second via holes are tapering toward the second conductor layer.

Abstract translation: 一种多层印刷电路板，包括第一绝缘层，在第一绝缘层的一个表面上具有导体电路的第一导体层，在第一绝缘层的相对表面上具有导体电路的第二导体层，第二绝缘层 在第二导体和第一绝缘层上的第二绝缘层和在第二导体层的相对侧的第二绝缘层上具有导体电路的第三导体层。 第一绝缘层和第二绝缘层具有第一和第二通孔，其形成在第一和第二绝缘层的开口中，并由填充到开口顶部的导电材料制成，使得第一和第三导体层中的导体电路连接到 第二导体层中的一个或多个导体电路，以及第一和第二通孔朝向第二导体层逐渐变细。

公开(公告)号：US07832098B2

公开(公告)日：2010-11-16

申请号：US12098582

申请日：2008-04-07

Applicant: Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

Inventor： Naohiro Hirose ,  Kouta Noda ,  Hiroshi Segawa ,  Honjin En ,  Kiyotaka Tsukada ,  Naoto Ishida ,  Kouji Asano ,  Atsushi Shouda

IPC: H01K3/10

CPC classification number: H05K3/4652 ,  B23K26/389 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H05K1/0201 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/0055 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/28 ,  H05K3/381 ,  H05K3/383 ,  H05K3/384 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/0358 ,  H05K2201/062 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/09881 ,  H05K2203/0307 ,  H05K2203/0353 ,  H05K2203/0554 ,  H05K2203/0773 ,  H05K2203/107 ,  H05K2203/121 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: An opening is formed in resin 20 by a laser beam so that a via hole is formed. At this time, copper foil 22, the thickness of which is reduced (to 3 μm) by performing etching to lower the thermal conductivity is used as a conformal mask. Therefore, an opening 20a can be formed in the resin 20 if the number of irradiation of pulse-shape laser beam is reduced. Therefore, occurrence of undercut of the resin 20 which forms an interlayer insulating resin layer can be prevented. Thus, the reliability of the connection of the via holes can be improved.

Abstract translation: 通过激光束在树脂20中形成开口，从而形成通孔。 此时，通过进行蚀刻来降低导热率的铜箔22的厚度（3μm）被用作保形掩模。 因此，如果脉冲形激光束的照射次数减少，则可以在树脂20中形成开口20a。 因此，可以防止形成层间绝缘树脂层的树脂20的底切的发生。 因此，可以提高通孔连接的可靠性。

公开(公告)号：US20100200154A1

公开(公告)日：2010-08-12

申请号：US12763204

申请日：2010-04-19

Applicant: Tsung-Yuan Chen

Inventor： Tsung-Yuan Chen

IPC: H05K3/46 ,  B32B38/00

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/0361 ,  H05K2203/0723 ,  Y10T29/49155 ,  Y10T156/1028

Abstract: A process for fabricating a circuit board with an embedded passive component is provided. An electrode-patterned layer having electrodes is formed on a surface of a conductive layer. A passive component material is filled in the intervals between the electrodes. The conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. The conductive layer is patterned to form a circuit layer.

Abstract translation: 提供了一种用于制造具有嵌入式无源元件的电路板的工艺。 具有电极的电极图案层形成在导电层的表面上。 无源部件材料被填充在电极之间的间隔中。 导电层和电极图案层层压到电介质层上，其中电极图案层被嵌入电介质层中。 将导电层图案化以形成电路层。

公开(公告)号：US20100187003A1

公开(公告)日：2010-07-29

申请号：US12649501

申请日：2009-12-30

Applicant: Kun-Chen Tsai

Inventor： Kun-Chen Tsai

IPC: H05K1/11 ,  H05K3/42

CPC classification number: H05K3/205 ,  H01L2924/0002 ,  H05K3/423 ,  H05K3/465 ,  H05K3/4682 ,  H05K2201/09563 ,  H05K2201/09881 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided are a circuit board structure and a fabrication method thereof, including the steps of: forming a first circuit layer in a first dielectric layer and exposing the first circuit layer therefrom; forming a second dielectric layer on the first dielectric layer and the first circuit layer, and forming a second circuit layer on the second dielectric layer; forming a plurality of first conductive vias in the second dielectric layer for electrically connecting to the first circuit layer to thereby dispense with a core board and electroplated holes and thus facilitate miniaturization. Further, the first dielectric layer is liquid before being hardened and is formed on the first dielectric layer that enhances the bonding between layers of the circuit board and the structure.

Abstract translation: 提供一种电路板结构及其制造方法，包括以下步骤：在第一电介质层中形成第一电路层，并从其露出第一电路层; 在所述第一电介质层和所述第一电路层上形成第二电介质层，以及在所述第二电介质层上形成第二电路层; 在第二电介质层中形成多个第一导电通孔，用于电连接到第一电路层，从而省去芯板和电镀孔，从而便于小型化。 此外，第一电介质层在硬化之前是液体，并且形成在增强电路板的层之间的结合的第一电介质层和结构之间。

公开(公告)号：US07733662B2

公开(公告)日：2010-06-08

申请号：US11626379

申请日：2007-01-24

Applicant: Tsung-Yuan Chen

Inventor： Tsung-Yuan Chen

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4611 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09236 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/0361 ,  H05K2203/0723 ,  Y10T29/49155 ,  Y10T156/1028

Abstract: A process for fabricating a circuit board with an embedded passive component is provided. First, an electrode-patterned layer having electrodes is formed on a surface of a conductive layer. Then, a passive component material is filled in the intervals between the electrodes. Then, the conductive layer and the electrode-patterned layer are laminated to a dielectric layer, wherein the electrode-patterned layer is embedded in the dielectric layer. Next, the conductive layer is patterned to form a circuit layer.

Abstract translation: 提供了一种用于制造具有嵌入式无源元件的电路板的工艺。 首先，在导电层的表面上形成具有电极的电极图案层。 然后，在电极之间的间隔中填充无源部件材料。 然后，将导电层和电极图案层层压到电介质层，其中电极图案层被嵌入在电介质层中。 接下来，对导电层进行图案化以形成电路层。

公开(公告)号：US07716825B2

公开(公告)日：2010-05-18

申请号：US10538505

申请日：2002-12-09

Applicant: Keiichi Murakami

Inventor： Keiichi Murakami

IPC: H05K3/02 ,  H05K3/10

CPC classification number: H05K3/28 ,  H05K2201/09881 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/085 ,  H05K2203/1152 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A method for manufacturing a printed wiring board, including forming a thermosetting resin layer on the printed wiring board; heating and curing the resin layer; and then polishing the cured resin layer, thereby exposing the circuit patterns. Additionally, the step of heating and curing includes maintaining the resin layer at a non-curable temperature in a state where the resin layer is pressed via the smoothing plate in a reduced pressure chamber; heating the resin layer in the pressed state to a curing temperature; introducing outside air into the reduced pressure chamber with the pressed state and the curing temperature maintained; reducing the pressure applied to the smoothing plate with the curing temperature maintained; and cooling the resin layer.

Abstract translation: 一种制造印刷线路板的方法，包括在印刷线路板上形成热固性树脂层; 加热和固化树脂层; 然后对固化的树脂层进行抛光，从而露出电路图案。 此外，加热和固化步骤包括在树脂层在减压室中经由平滑板压制的状态下将树脂层保持在不可固化温度; 将处于压制状态的树脂层加热至固化温度; 将外部空气以压制状态引入减压室并维持固化温度; 降低施加到平滑板上的压力，同时保持固化温度; 并冷却树脂层。

公开(公告)号：US20100078208A1

公开(公告)日：2010-04-01

申请号：US12585754

申请日：2009-09-24

Applicant: Seiichi Inoue

Inventor： Seiichi Inoue

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/246 ,  H05K1/0256 ,  H05K1/036 ,  H05K3/0032 ,  H05K3/1208 ,  H05K3/125 ,  H05K3/28 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2201/0761 ,  H05K2201/0769 ,  H05K2201/09036 ,  H05K2201/09881 ,  H05K2203/013 ,  H05K2203/1147 ,  H05K2203/1173 ,  Y10T29/49155

Abstract: A method of forming a wiring board comprises: a step of forming a receptive layer having a porous structure on a substrate; a step of forming wiring portions in a desired conductive pattern on a surface of the receptive layer by ejecting a colloidal metal solution for drawing by an ink-jet system based on image date of the conductive pattern; and a step of performing a migration-proof treatment on at least part of the receptive layer exposed between mutually adjacent wiring portions.

Abstract translation: 形成布线板的方法包括：在基板上形成具有多孔结构的接收层的步骤; 基于导电图案的图像日期，通过喷射通过喷墨系统进行拉伸的胶体金属溶液，在接收层的表面上形成所需导电图案中的布线部分的步骤; 以及对相互相邻的布线部之间露出的接受层的至少一部分进行防迁移处理的步骤。

公开(公告)号：US07676913B2

公开(公告)日：2010-03-16

申请号：US12016826

申请日：2008-01-18

Applicant: Hideo Imai ,  Kazuaki Sakurada

Inventor： Hideo Imai ,  Kazuaki Sakurada

IPC: H05K3/30

CPC classification number: H05K3/4664 ,  H05K1/0393 ,  H05K3/108 ,  H05K3/125 ,  H05K3/184 ,  H05K3/4685 ,  H05K2201/09881 ,  H05K2203/013 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A method of manufacturing a wiring board includes steps of: providing a substrate; forming a first wiring layer on the substrate by photolithography; forming a first insulating layer by ink jetting so as to cover a part of the first wiring layer and expose an exposed section of the first wiring layer; and forming a second wiring layer by ink jetting partly over the first wiring layer, with the first insulating layer being between the part of the first wiring layer and a part of the second wiring layer. A wider variety of conductive material and insulating material can be used for forming the wiring layers and the insulating layers on the substrate by ink jetting, while the wiring board has a first wiring layer having high density.

Abstract translation: 制造布线板的方法包括以下步骤：提供基板; 通过光刻在基板上形成第一布线层; 通过喷墨形成第一绝缘层，以覆盖第一布线层的一部分并暴露第一布线层的暴露部分; 以及通过部分地在所述第一布线层上的喷墨形成第二布线层，所述第一绝缘层位于所述第一布线层的所述部分和所述第二布线层的一部分之间。 可以使用更多种导电材料和绝缘材料来通过喷墨形成布线层和基板上的绝缘层，同时布线板具有高密度的第一布线层。

公开(公告)号：US07674672B2

公开(公告)日：2010-03-09

申请号：US12358852

申请日：2009-01-23

Applicant: Shih-Lian Cheng

Inventor： Shih-Lian Cheng

IPC: H01L21/8234 ,  H01L21/8244 ,  H01L21/20 ,  H01L21/44

CPC classification number: H05K1/165 ,  H05K1/092 ,  H05K1/167 ,  H05K1/183 ,  H05K3/427 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/086 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/1147 ,  H05K2203/1453

Abstract: A fabricating process for a substrate with an embedded passive component is provided. The fabricating process includes the following steps. First, a substrate including a top conductive layer, a bottom conductive layer, and at least a dielectric layer is provided. The top conductive layer and the bottom conductive layer are separately disposed on a top surface and a bottom surface of the dielectric layer. Next, a plurality of plating through holes is formed in the substrate. Then, the top and the bottom conductive layers are patterned to form a patterned top conductive layer and a patterned bottom conductive layer separately, and the dielectric layer is exposed in part. The patterned top conductive layer and the patterned bottom conductive layer have many traces and many trenches formed by the traces. Thereafter, the trenches are filled with a material, wherein the traces and the material are adapted for forming the passive component.

Abstract translation: 提供了一种具有嵌入式无源元件的基板的制造工艺。 制造过程包括以下步骤。 首先，提供包括顶部导电层，底部导电层和至少介电层的基板。 顶导电层和底导电层分别设置在电介质层的顶表面和底表面上。 接下来，在基板上形成多个电镀通孔。 然后，对顶部和底部导电层进行图案化以分别形成图案化的顶部导电层和图案化的底部导电层，并且介电层部分暴露。 图案化的顶部导电层和图案化的底部导电层具有许多迹线和由迹线形成的许多沟槽。 此后，沟槽填充有材料，其中迹线和材料适于形成无源部件。