公开(公告)号：US20110279990A1

公开(公告)日：2011-11-17

申请号：US13145768

申请日：2009-02-26

Applicant: Makoto Hirano

Inventor： Makoto Hirano

IPC: H05K1/02

CPC classification number: H05K1/111 ,  H05K1/141 ,  H05K3/3442 ,  H05K2201/094 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2203/0465 ,  Y02P70/611 ,  Y02P70/613

Abstract: A printed board includes footprints which are electrically solder-bonded to a surface-mounting substrate, on which electronic components are mounted, and which assists the heat release from the surface-mounting substrate. The footprint comprises a fillet-forming division which is placed on an outer-edge side of the surface-mounting substrate and where solder is supplied independently when solder-bonding is performed. The fillet-forming division is solder-bonded to the same electrode as the electrode of the surface-mounting substrate to which the footprint is solder-bonded.

Abstract translation: 印刷电路板包括与焊接到表面安装基板上的电焊焊接，其上安装有电子部件，并且有助于从表面安装基板释放热量。 占地面积包括一个放置在表面安装基板的外边缘侧的焊脚形成部分，并且在进行焊接时独立地供应焊料。 圆角形成部分焊接到与焊接焊点的表面安装基板的电极相同的电极上。

公开(公告)号：US07969261B2

公开(公告)日：2011-06-28

申请号：US12392504

申请日：2009-02-25

Applicant: Norio Okada

Inventor： Norio Okada

IPC: H01P3/08

CPC classification number: H01P3/081 ,  H05K1/0219 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0239 ,  H05K1/025 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663

Abstract: A transmission line substrate includes: a dielectric substrate; a signal line disposed on the upper surface of the dielectric substrate; first and second ground conductors disposed on the upper surface of the dielectric substrate, field-coupled to the signal line, having potentials different from each other; a dielectric film disposed between an overlapping part of the first ground conductor and a part of the second ground conductor at which the first and second ground conductors overlap each other, to constitute a MIM capacitor; a capacitor connected between the first ground conductor and the second ground conductor in parallel with the dielectric film; and a resistor connected between the first ground conductor and the second ground conductor in series with the capacitor.

Abstract translation: 传输线基板包括：电介质基板; 设置在电介质基板的上表面上的信号线; 第一和第二接地导体，其设置在电介质基板的上表面上，场耦合到信号线，具有彼此不同的电位; 电介质膜，设置在所述第一接地导体的重叠部分与所述第二接地导体的所述第一接地导体和所述第二接地导体彼此重叠的部分之间，以构成MIM电容器; 电容器，其与所述电介质膜平行地连接在所述第一接地导体和所述第二接地导体之间; 以及连接在与电容器串联的第一接地导体和第二接地导体之间的电阻器。

公开(公告)号：US07967184B2

公开(公告)日：2011-06-28

申请号：US11280419

申请日：2005-11-16

Applicant: Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

Inventor： Chih-Chin Liao ,  Ken Jian Ming Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chang Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

IPC: B23K31/02

CPC classification number: H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

Abstract: A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

Abstract translation: 公开了一种具有低轮廓的半导体封装。 在实施例中，表面安装部件可以直接安装到半导体封装基板的芯部，使得在部件和基板芯之间不存在导电层，镀层或焊膏。 表面安装部件可以是根据SMT工艺可以表面安装在基板上的任何类型的部件，包括例如无源部件和各种封装半导体。

公开(公告)号：US20110139489A1

公开(公告)日：2011-06-16

申请号：US12772469

申请日：2010-05-03

Applicant: Hee-Soo Yoon ,  Dong-Hwan Lee ,  Kyoung-Ho Lee ,  Yoon-Dong Kim ,  Su-Bong Jang

Inventor： Hee-Soo Yoon ,  Dong-Hwan Lee ,  Kyoung-Ho Lee ,  Yoon-Dong Kim ,  Su-Bong Jang

IPC: H05K1/00

CPC classification number: H05K1/0227 ,  H05K1/0262 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09663

Abstract: A printed circuit board is disclosed. The printed circuit board in accordance with an embodiment of the present invention can include an insulation substrate, a first ground, which is formed on one surface of the insulation substrate and connected to a first power source, a second ground, which is formed on one surface of the insulation substrate and connected to a second power source, a separator, which separates the first ground from the second ground, a first signal line, which is stacked on at least one of the first ground and the second ground, and a second signal line, which is stacked on at least one of the first ground and the second ground and is adjacent to the first signal line. The separator can include a curved part, which is bent in between the first signal line and the second signal line.

Abstract translation: 公开了印刷电路板。 根据本发明的实施例的印刷电路板可以包括绝缘基板，第一接地，其形成在绝缘基板的一个表面上并连接到第一电源，第二接地形成在第一接地 绝缘基板的表面并且连接到第二电源，将第一接地与第二接地分离的隔离件，堆叠在第一接地和第二接地中的至少一个上的第一信号线，以及第二接地 信号线，其堆叠在第一接地和第二接地中的至少一个上并且与第一信号线相邻。 分离器可以包括在第一信号线和第二信号线之间弯曲的弯曲部分。

公开(公告)号：US07952202B2

公开(公告)日：2011-05-31

申请号：US11847985

申请日：2007-08-30

Applicant: Todd B Myers ,  Nicholas R. Watts ,  Eric C Palmer ,  Jui Min Lim

Inventor： Todd B Myers ,  Nicholas R. Watts ,  Eric C Palmer ,  Jui Min Lim

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US07901248B2

公开(公告)日：2011-03-08

申请号：US12386641

申请日：2009-04-21

Applicant: Juergen Lappoehn

Inventor： Juergen Lappoehn

IPC: H01R13/648

CPC classification number: H05K1/0219 ,  H01R12/716 ,  H01R12/724 ,  H01R13/6585 ,  H05K1/0237 ,  H05K3/308 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10189 ,  H05K2201/1059

Abstract: A multipolar plug connector for establishing contact with a multilayer board includes signal contacts that are assigned a first and at least one second screen contact element and are arranged adjacent to the signal contact. Recesses are provided at least on the uppermost Layer of the multilayer board which are suitably sized so as to receive and to lead through at least two screen contact elements assigned to neighboring signal contacts.

Abstract translation: 用于与多层板建立接触的多极插头连接器包括被分配有第一和至少一个第二屏幕接触元件并被布置成与信号触点相邻的信号触点。 至少在多层板的最上层设置有适当尺寸以便接收和引导分配给相邻信号触点的至少两个屏幕接触元件的凹陷。

公开(公告)号：US07873933B2

公开(公告)日：2011-01-18

申请号：US11936673

申请日：2007-11-07

Applicant: Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

Inventor： Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

IPC: G06F17/50 ,  H03K17/693

CPC classification number: H05K1/0265 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10189 ,  Y10T29/49156

Abstract: A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract translation: 用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。 在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。 连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。 槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。 所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

公开(公告)号：US07872874B2

公开(公告)日：2011-01-18

申请号：US11701816

申请日：2007-02-01

Applicant: Jun Karasawa ,  Daigo Suzuki ,  Hidenori Tanaka

Inventor： Jun Karasawa ,  Daigo Suzuki ,  Hidenori Tanaka

IPC: H05K7/10 ,  H05K7/12

CPC classification number: H05K1/111 ,  H05K3/284 ,  H05K3/3421 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49147

Abstract: According to one embodiment, there is provided a printed-wiring board with a component in which an electronic component is mounted on a pattern-forming surface of a base material. In the printed-wiring board, a guiding path for guiding, to the outside, a void formed in mounting the electronic component is formed on the pattern-forming surface.

Abstract translation: 根据一个实施例，提供了一种印刷电路板，其具有将电子部件安装在基材的图案形成表面上的部件。 在印刷电路板中，在图案形成表面上形成用于将安装电子部件形成的空隙引导到外部的引导路径。

公开(公告)号：US07797663B2

公开(公告)日：2010-09-14

申请号：US11696659

申请日：2007-04-04

Applicant: Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

Inventor： Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

IPC: G06F17/50

CPC classification number: G01R31/2818 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0262 ,  H05K1/0268 ,  H05K1/113 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3457 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0367 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/10333 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (μVia) having a conductive dome disposed above the outer layer pad of the μVia. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.

Abstract translation: 提供了使用高密度互连（HDI技术）访问在印刷电路板（PCB）的内层上的导电迹线上路由的高速信号的方法和装置。 导电迹线可以耦合到具有设置在μVia的外层焊盘上方的导电圆顶的微孔（μVia）。 与使用电镀通孔（PTH）技术的常规测试点相比，在线测试（ICT）固定装置或高速测试探头可与导电圆顶接口以测试具有降低的反射损耗和其他寄生效应的高速信号。

公开(公告)号：US20100220455A1

公开(公告)日：2010-09-02

申请号：US12775766

申请日：2010-05-07

Applicant: MING-TAN HSU ,  I-CHENG SHIH

Inventor： MING-TAN HSU ,  I-CHENG SHIH

IPC: H05K1/14

CPC classification number: G01R31/026 ,  G01R31/046 ,  H05K1/0268 ,  H05K1/117 ,  H05K3/323 ,  H05K3/361 ,  H05K2201/09663

Abstract: The present invention provides a bonding structure of circuit substrates for instant circuit inspecting. The contact pad design of the bonding structure has an instant inspection ability of circuit connection in bonding two circuit substrates. In two bonded circuit substrates, the signal inputted at the circuit part passes the conductive particles to the first contact pad, and then passes the conductive particles again to the detecting part from the first contact pad. Therefore, measuring the output signal can inspect the reliability of the circuit connection of the bonded circuit substrates. If the output signal is the same as the input signal, the bonding structure between the first contact pad and the circuit part is validated, or, if not, the bonding structure is invalidated.

Abstract translation: 本发明提供用于即时电路检查的电路基板的接合结构。 接合结构的接触焊盘设计具有连接两个电路基板时的电路连接的即时检测能力。 在两个接合电路基板中，输入到电路部分的信号将导电粒子传递到第一接触焊盘，然后从第一接触焊盘再次将导电粒子传递到检测部分。 因此，测量输出信号可以检测接合电路基板的电路连接的可靠性。 如果输出信号与输入信号相同，则验证第一接触焊盘与电路部分之间的接合结构，否则，接合结构无效。