公开(公告)号：US20050145595A1

公开(公告)日：2005-07-07

申请号：US10707640

申请日：2003-12-29

Applicant: Jose Cubero Pitel

Inventor： Jose Cubero Pitel

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/28 ,  H01B13/00

CPC classification number: H05K3/28 ,  H05K1/0263 ,  H05K3/06 ,  H05K2201/0195 ,  H05K2201/098 ,  H05K2201/09881 ,  H05K2203/1121

Abstract: It comprises the steps of: a) arranging a dielectric substrate (1) with at least one conducting plate (2) joined by an adhesive (8) to at least one of its sides; b) removing areas of said plate (2) by selective chemical milling to provide conducting tracks (5) joined to the substrate (1) and separated by spaces between tracks (6); c) applying and hardening by radiation an electroinsulating filler material (7) to fill said spaces between tracks (6), covering the tracks (5); d) applying an abrasion treatment to obtain flush upper surfaces (3) of the filler material (7) and of the tracks; and e) cooling, after step c) and during step d), the printed circuit board to reduce the temperature of the filler material (7) to under its glass transition temperature.

Abstract translation: 它包括以下步骤：a）将具有至少一个导电板（2）的介电基片（1）布置成由粘合剂（8）连接到其至少一个侧面; b）通过选择性化学研磨去除所述板（2）的区域，以提供连接到基板（1）并由轨道（6）之间的间隔分隔的导电轨道（5）; c）通过辐射施加和硬化电绝缘填充材料（7）以填充覆盖轨道（5）的轨道（6）之间的所述空间; d）进行磨损处理以获得填充材料（7）和轨道的平齐的上表面（3）; 和e）在步骤c）之后和步骤d）期间冷却印刷​​电路板，以将填料（7）的温度降低到其玻璃化转变温度以下。

公开(公告)号：US20050017058A1

公开(公告)日：2005-01-27

申请号：US10710561

申请日：2004-07-21

Applicant: Kwun-Yao Ho ,  Moriss Kung

Inventor： Kwun-Yao Ho ,  Moriss Kung

IPC: B23K1/00 ,  B23K1/19 ,  B23K1/20 ,  H01L21/48 ,  H05K3/24 ,  H05K3/28 ,  B23K31/02

CPC classification number: H01L21/4857 ,  B23K1/0018 ,  B23K1/19 ,  B23K1/20 ,  B23K2101/42 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0195 ,  H05K2201/0352 ,  H05K2201/09436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09881 ,  H05K2203/054 ,  H05K2203/0542

Abstract: The present invention provides a method of fabricating a circuit substrate. First, a substrate having first pads and second pads is provided, wherein the first pads and second pads are arranged respectively on a first surface and a second surface of the substrate. The first pads are electrically connected to the second pads. Next, a conductive seed layer is formed on the second surface of the circuit substrate. Thereafter, a first conductive layer and a second conductive layer are electroplated respectively over the first pads and the second pads. Afterwards, the conductive seed layer is patterned.

Abstract translation: 本发明提供一种制造电路基板的方法。 首先，提供具有第一焊盘和第二焊盘的衬底，其中第一焊盘和第二焊盘分别布置在衬底的第一表面和第二表面上。 第一焊盘电连接到第二焊盘。 接下来，在电路基板的第二表面上形成导电种子层。 此后，分别在第一焊盘和第二焊盘上电镀第一导电层和第二导电层。 之后，对导电种子层进行图案化。

公开(公告)号：US06801437B2

公开(公告)日：2004-10-05

申请号：US10347759

申请日：2003-01-21

Applicant: Maurice O. Othieno ,  Manickam Thavarajah ,  Severino A. Legaspi, Jr. ,  Pradip D. Patel

Inventor： Maurice O. Othieno ,  Manickam Thavarajah ,  Severino A. Legaspi, Jr. ,  Pradip D. Patel

IPC: H05K118

CPC classification number: H05K3/28 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/243 ,  H05K2201/0195 ,  H05K2201/09881 ,  H05K2203/0759

Abstract: A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers. Both the second layer and the third layer of photo imageable ink are retained on the electronic substrate.

公开(公告)号：US06800936B2

公开(公告)日：2004-10-05

申请号：US10332015

申请日：2003-01-03

Applicant: Takahiko Kosemura ,  Akihiko Okubora ,  Takayuki Hirabayashi ,  Tatsuya Ogino ,  Kuniyuki Hayashi

Inventor： Takahiko Kosemura ,  Akihiko Okubora ,  Takayuki Hirabayashi ,  Tatsuya Ogino ,  Kuniyuki Hayashi

IPC: H01L2324

CPC classification number: H01L23/66 ,  H01F17/0006 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01087 ,  H05K1/165 ,  H05K3/4602 ,  H05K3/4664 ,  H05K3/467 ,  H05K2201/0195 ,  H05K2201/09881

Abstract: The present invention provides a high-frequency module configuring a micro communication functional module, which includes a base substrate (2) which has multiple pattern wiring layers (6a) (6b) (9a) (9b) and dielectric insulating layers (5) (8) (11) formed therein, and has a buildup surface for smoothing the upper layer thereof, and a high-frequency element layer (4) formed on the buildup surface, which has an inductor (20) formed therein via an insulating layer (19) formed on the buildup surface. The base substrate (2) is provided with a region (30) where the pattern wiring layers (6a) (6b) (9a) (9b) are not formed from the upper layer to at least the mid portion thereof along the thickness direction, and the inductor (20) of the high-frequency element layer (4) is formed directly above the region (30).

Abstract translation: 本发明提供构成微通信功能模块的高频模块，其包括具有多个图案布线层（6a）（6b）（9a）（9b）和介电绝缘层（5）的基底（2） 8）（11），并且具有用于使其上层平坦化的积层表面和形成在积累表面上的高频元件层（4），该高频元件层（4）具有经由绝缘层形成在其中的电感器（20） 19）形成在积聚表面上。 基底基板（2）具有区域（30），其中图形布线层（6a）（6b）（9a）（9b））不沿着厚度方向至少至少其中间部分形成， 并且高频元件层（4）的电感器（20）直接形成在区域（30）的正上方。

公开(公告)号：US06717067B2

公开(公告)日：2004-04-06

申请号：US10198341

申请日：2002-07-18

Applicant: Zhong-You Shi ,  Delin Li ,  Richard McMillan

Inventor： Zhong-You Shi ,  Delin Li ,  Richard McMillan

IPC: H01R1204

CPC classification number: H05K3/429 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4038 ,  H05K3/4069 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K3/4685 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09845 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A method 10, 110 for making multi-layer circuit boards having metallized apertures 38, 40, 130, 132 which may be selectively and electrically grounded and having at least one formed air-bridge 92, 178.

Abstract translation: 一种用于制造具有金属化孔38,40,130,132的多层电路板的方法10,110，其可以选择性地和电接地并且具有至少一个形成的空气桥92,178。

公开(公告)号：US20040003943A1

公开(公告)日：2004-01-08

申请号：US10612990

申请日：2003-07-07

Applicant: FUJITSU LIMITED

Inventor： Kenji IIda

IPC: H05K001/11

CPC classification number: H05K3/108 ,  H05K3/045 ,  H05K3/243 ,  H05K3/4647 ,  H05K2201/09881 ,  H05K2203/025 ,  H05K2203/054 ,  H05K2203/0542 ,  H05K2203/0733 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: In the multilayer circuit board, cable patterns in a plurality of cable layers can be precisely formed, and the cable layer are formed with higher density, with higher reliability. The multilayer circuit board comprises: a plurality of cable layers, each of which includes electric conductive sections; a plurality of first insulating layers, each of which encloses the electric conductive sections in each cable layer and fills spaces between the electric conductive sections; and post vias electrically connecting the electric conductive sections in one cable layer to those in another cable layer. Height of the electric conductive sections in each cable layer are equal to that of the first insulating layer enclosing those electric conductive sections.

Abstract translation: 在多层电路板中，可以精确地形成多个电缆层中的电缆图案，并且以更高的可靠性形成更高密度的电缆层。 多层电路板包括：多个电缆层，每个电缆层包括导电部分; 多个第一绝缘层，每个绝缘层包围每个电缆层中的导电部分，并填充导电部分之间的空间; 以及将一个电缆层中的导电部分电连接到另一电缆层中的导电部分的通孔。 每个电缆层中的导电部分的高度等于封装这些导电部分的第一绝缘层的高度。

公开(公告)号：US20030222340A1

公开(公告)日：2003-12-04

申请号：US10437041

申请日：2003-05-14

Inventor： Koji Kondo ,  Ryohei Kataoka ,  Gentaro Masuda

IPC: H01L023/053 ,  H01L023/12

CPC classification number: H05K3/4632 ,  H01L23/498 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/4069 ,  H05K3/4617 ,  H05K2201/0129 ,  H05K2201/0394 ,  H05K2201/09881 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A multilayer circuit board, in which a plurality of insulating layers and a plurality of conductive layers, each of which includes a conductive pattern, have been laminated, includes an insulating layer, a conductive compound, and a conductive pattern. The insulating layer has a trench. The conductive compound is located in the trench. The conductive pattern adjoins the trench and is electrically connected to the conductive compound. The conductive pattern and the conductive compound make up a conductive wire that has a higher current-carrying capacity than the conductive pattern.

Abstract translation: 层叠有多个绝缘层和多个导体层的多层电路基板，其中，所述多个绝缘层和多个导体层包含导体图案，其中包括绝缘层，导电性化合物和导体图案。 绝缘层具有沟槽。 导电化合物位于沟槽中。 导电图案与沟槽相邻并且与导电化合物电连接。 导电图案和导电化合物组成导电线，其具有比导电图案更高的载流能力。

公开(公告)号：US06584682B2

公开(公告)日：2003-07-01

申请号：US09812345

申请日：2001-03-20

Applicant: Robert Edward Belke ,  Thomas Bernd Krautheim ,  Vivek Amir Jairazbhoy ,  Delin Li

Inventor： Robert Edward Belke ,  Thomas Bernd Krautheim ,  Vivek Amir Jairazbhoy ,  Delin Li

IPC: H05K320

CPC classification number: H05K3/4038 ,  H05K3/0047 ,  H05K3/06 ,  H05K3/062 ,  H05K3/064 ,  H05K3/4069 ,  H05K3/429 ,  H05K3/44 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4611 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0305 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/0379 ,  H05K2201/0397 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/066 ,  H05K2203/0733 ,  H05K2203/1152 ,  H05K2203/1184 ,  H05K2203/1536 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method 10 for making multi-layer electronic circuit boards 148, 248 having aperture 146, 246 which may be selectively connected to an electrical ground potential.

Abstract translation: 一种用于制造具有孔146,246的多层电子电路板148,248的方法10，其可选择性地连接到电接地电位。

公开(公告)号：US06542379B1

公开(公告)日：2003-04-01

申请号：US09353992

申请日：1999-07-15

Applicant: John M. Lauffer ,  David J. Russell

Inventor： John M. Lauffer ,  David J. Russell

IPC: H05K116

CPC classification number: H01F41/041 ,  H01F17/0033 ,  H05K1/095 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/0023 ,  H05K3/386 ,  H05K3/4069 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/086 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/09881 ,  H05K2203/0568 ,  H05K2203/1453 ,  H05K2203/1461 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T428/24917 ,  Y10T428/2495 ,  Y10T428/24967 ,  Y10T428/24975

Abstract: Passive electrical components such as capacitors, resistors, inductors, transformers, filters and resonators are integrated in to electrical circuits utilizing a process which maximizes the utilization of the planar surfaces of the substrates for high density placement of active components such as logic or memory integrated circuits. The passive components are integrated into a conventional circuit board utilizing a photoimageable dielectric material. The dielectric is photoimaged and etched to provide one or more recesses or openings for the passive devices, and photovias interconnecting the inputs and outputs of the integrated circuit board. The electronic structure comprising at least one of the passive devices integrated into a photoimaged dielectric is described as well as the method of manufacturing the same.

Abstract translation: 电容器，电阻器，电感器，变压器，滤波器和谐振器等被动电气元件集成到电路中，利用最大限度地利用衬底的平面来进行高密度放置有源元件例如逻辑或存储器集成电路 。 将无源部件集成到利用可光成像的电介质材料的常规电路板中。 电介质被光刻和蚀刻以提供用于无源器件的一个或多个凹部或开口，以及互连集成电路板的输入和输出的光电隔离。 描述了包括集成到光电介质中的无源器件中的至少一个的电子结构及其制造方法。

公开(公告)号：US20020149101A1

公开(公告)日：2002-10-17

申请号：US10118744

申请日：2002-04-09

Applicant: NGK Insulators, Ltd.

Inventor： Koji Ikeda ,  Kazuyoshi Shibata

IPC: H01L023/495 ,  H01L023/06 ,  H01L023/10 ,  H01L023/15

CPC classification number: H05K3/38 ,  H01L41/047 ,  H01L41/0471 ,  H01L41/0477 ,  H01L41/094 ,  H01L41/273 ,  H01L41/29 ,  H01L41/314 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K1/16 ,  H05K3/4667 ,  H05K2201/0175 ,  H05K2201/09881 ,  H05K2201/10083 ,  H01L2924/00

Abstract: A first cermet layer to be a first wiring pattern and a second cermet layer to be an insulating layer filling gaps in the first wiring pattern are formed on a ceramic substrate. Thereafter, the first cermet layer and the second cermet layer are fired to produce the first wiring pattern and the insulating layer simultaneously. Then, a PZT paste to be a piezoelectric/electrostrictive layer is formed and thereafter fired to produce the piezoelectric/electrostrictive layer. Thereafter, a third cermet layer to be a second wiring pattern is formed and thereafter fired to produce the second wiring pattern, thereby fabricating a wiring board.

Abstract translation: 作为第一布线图案的第一金属陶瓷层和填充第一布线图案中的间隙的绝缘层的第二金属陶瓷层形成在陶瓷基板上。 此后，第一金属陶瓷层和第二金属陶瓷层被烧制以同时产生第一布线图案和绝缘层。 然后，形成作为压电/电致伸缩层的PZT糊料，然后烧制以产生压电/电致伸缩层。 此后，形成作为第二布线图案的第三金属陶瓷层，然后烧制以产生第二布线图案，从而制造布线板。