公开(公告)号：US09433107B2

公开(公告)日：2016-08-30

申请号：US14365920

申请日：2012-12-12

Applicant: LG INNOTEK CO., LTD.

Inventor： Hyun Seok Seo ,  Ki Do Chun ,  Sang Myung Lee ,  Yeong Uk Seo ,  Chang Woo Yoo ,  Byeong Ho Kim

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/46 ,  H05K1/02 ,  H05K3/06 ,  H05K1/09

CPC classification number: H05K3/4644 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/06 ,  H05K3/465 ,  H05K2201/0376 ,  H05K2201/09781 ,  H05K2201/10204 ,  H05K2203/0353

Abstract: Provided is a printed circuit board, including a plurality of buried circuit patterns which are formed in an active area; and a plurality of buried dummy patterns which are uniformly formed in a dummy area except the active area. Thus, since when the circuit patterns are formed, the dummy patterns are also uniformly formed, a difference in plating can be reduced. Also, since the dummy patterns are uniformly formed in the dummy area, a difference in grinding between the dummy area and the active area can be reduced, thereby enabling the circuit patterns to be formed in the active area without the occurrence of over-grinding.

Abstract translation: 提供一种印刷电路板，包括形成在有源区域中的多个掩埋电路图案; 以及均匀地形成在除了有效区域之外的虚拟区域中的多个埋置的虚设图案。 因此，由于当形成电路图案时，也可以均匀地形成虚设图案，可以减少电镀差异。 此外，由于虚拟图案均匀地形成在虚拟区域中，所以可以减少虚设区域和有效区域之间的磨削差异，从而能够在有源区域中形成电路图案而不会发生过磨削。

公开(公告)号：US09433074B2

公开(公告)日：2016-08-30

申请号：US14038834

申请日：2013-09-27

Applicant: Toyota Motor Engineering & Manufacturing North America, Inc.

Inventor： Ercan Mehmet Dede ,  Tsuyoshi Nomura ,  Paul Schmalenberg ,  Jae Seung Lee

IPC: H05K1/00 ,  H05K1/02

CPC classification number: H05K1/0203 ,  H05K1/0209 ,  H05K2201/0376 ,  H05K2201/09718 ,  H05K2201/09972 ,  H05K2201/10553

Abstract: A printed wiring board includes an insulator substrate, an electrical conductor at least partially embedded in the insulator substrate, and a thermal conductor at least partially embedded in the insulator substrate. The printed wiring board also includes a temperature-insensitive component mounting region and a temperature-sensitive component mounting region. The insulator substrate and the thermal conductor are arranged into a targeted heat transfer region proximate to the temperature-sensitive component mounting region and a bulk region at positions spaced apart from the temperature-sensitive component mounting region.

Abstract translation: 印刷电路板包括绝缘体基板，至少部分地嵌入在绝缘体基板中的电导体和至少部分地嵌入绝缘体基板中的热导体。 印刷线路板还包括温度不敏感元件安装区域和温度敏感元件安装区域。 绝缘体基板和热导体被布置成靠近感温元件安装区域的目标传热区域和与感温元件安装区域间隔开的位置处的主体区域。

公开(公告)号：US09426885B2

公开(公告)日：2016-08-23

申请号：US14261465

申请日：2014-04-25

Applicant: Todd Mathew Spath ,  Ronald Steven Cok

Inventor： Todd Mathew Spath ,  Ronald Steven Cok

IPC: H05K1/09 ,  H05K3/24 ,  G06F3/044 ,  G06F3/041 ,  H05K1/18

CPC classification number: H05K1/097 ,  G06F3/047 ,  G06F2203/04103 ,  G06F2203/04112 ,  H05K1/189 ,  H05K3/1258 ,  H05K3/247 ,  H05K2201/0108 ,  H05K2201/0329 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0108 ,  H05K2203/1545

Abstract: A multi-layer micro-wire structure resistant to cracking including a substrate having a surface, one or more micro-channels formed in the substrate, an electrically conductive first material composition forming a first layer located in each micro-channel, and an electrically conductive second material composition having a greater tensile ductility than the first material composition forming a second layer located in each micro-channel, the first material composition and the second material composition in electrical contact to form an electrically conductive multi-layer micro-wire in each micro-channel, whereby the multi-layer micro-wire is resistant to cracking.

Abstract translation: 一种耐裂纹的多层微线结构，包括具有表面的基底，在基底中形成的一个或多个微通道，形成位于每个微通道中的第一层的导电第一材料组合物，以及导电 第二材料组合物具有比形成位于每个微通道中的第二层的第一材料组合物更大的拉伸延展性，第一材料组合物和第二材料组合物电接触以在每个微通道中形成导电多层微线 通道，由此多层微线耐开裂。

公开(公告)号：US20160234935A1

公开(公告)日：2016-08-11

申请号：US15015551

申请日：2016-02-04

Applicant: JX NIPPON MINING & METALS CORPORATION

Inventor： MICHIYA KOHIKI

IPC: H05K1/09 ,  H05K3/00

CPC classification number: H05K1/09 ,  C23C18/1653 ,  C25D1/04 ,  C25D3/04 ,  C25D3/18 ,  C25D3/38 ,  C25D3/562 ,  C25D5/14 ,  C25D7/0614 ,  H05K3/0058 ,  H05K3/025 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/421 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K2203/0726

Abstract: Provided is a copper foil provided with a carrier in which the laser hole-opening properties of the ultrathin copper layer are good and which is suitable for producing a high-density integrated circuit substrate. A copper foil provided with a carrier having, in order, a carrier, an intermediate layer, and an ultrathin copper layer, wherein the specular gloss at 60° in an MD direction of the intermediate layer side surface of the ultrathin copper layer is 140 or less.

Abstract translation: 提供一种具有载体的铜箔，其中超薄铜层的激光开孔性能良好，适用于生产高密度集成电路基板。 具有依次具有载体，中间层和超薄铜层的载体的铜箔，其中在超薄铜层的中间层侧表面的MD方向上60°的镜面光泽度为140或 减。

公开(公告)号：US20160099204A1

公开(公告)日：2016-04-07

申请号：US14709510

申请日：2015-05-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-Fu Lin ,  Chin-Tsai Yao ,  Chia-Cheng Chen ,  Chih-Jen Yang ,  Fu-Tang Huang

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H05K1/11 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14131 ,  H01L2224/14133 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/17106 ,  H01L2224/81193 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/18161 ,  H01L2924/381 ,  H01L2924/3841 ,  H05K1/111 ,  H05K2201/0367 ,  H05K2201/0376 ,  H05K2201/09227 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package structure is provided, including: a board having a plurality of conductive traces; a plurality of conductive pads formed on the board and each having a height greater than a height of each of the conductive traces; and an electronic component disposed on and electrically connected to the conductive pads via a plurality of conductive elements, wherein at least one of the conductive traces is positioned in proximity of at least one of the conductive pads. Therefore, the conductive elements are prevented from being in contact with the conductive traces, and the problem that the conductive pads and the conductive traces are shorted is solved. The present invention further provides a method for fabricating the packaging substrate.

Abstract translation: 提供一种封装结构，包括：具有多个导电迹线的板; 多个导电焊盘，其形成在所述板上并且每个具有高于每个所述导电迹线的高度的高度; 以及电子部件，其经由多个导电元件设置在导电焊盘上并与其电连接，其中至少一个导电迹线位于至少一个导电焊盘附近。 因此，防止了导电元件与导电迹线接触，解决了导电焊盘和导电迹线短路的问题。 本发明还提供一种制造封装基板的方法。

公开(公告)号：US20160095215A1

公开(公告)日：2016-03-31

申请号：US14865050

申请日：2015-09-25

Applicant: IBIDEN CO., LTD.

Inventor： Toshiki Furutani

IPC: H05K1/09 ,  H05K3/07 ,  H05K1/11

CPC classification number: H05K1/09 ,  H05K1/0265 ,  H05K3/0097 ,  H05K3/4652 ,  H05K2201/0376 ,  H05K2201/096 ,  H05K2201/09727 ,  H05K2203/1536

Abstract: A printed wiring board includes a resin insulating layer, and a first conductor layer including a fine wiring pattern and a thick-film wiring pattern. The fine wiring pattern is embedded in the resin insulating layer such that the fine wiring pattern has an exposed surface exposed on a first surface of the resin insulating layer. The thick-film wiring pattern includes an embedded wiring portion and a thick-film wiring portion such that the embedded wiring portion is embedded in the resin insulating layer and the thick-film wiring portion is projecting from the first surface of the resin insulating layer. The embedded wiring portion of the thick-film wiring pattern has a line width which is greater than a line width of the fine wiring pattern.

Abstract translation: 印刷电路板包括树脂绝缘层和包括精细布线图案和厚膜布线图案的第一导体层。 精细布线图案嵌入在树脂绝缘层中，使得精细布线图案具有暴露在树脂绝缘层的第一表面上的暴露表面。 厚膜布线图案包括嵌入布线部分和厚膜布线部分，使得嵌入布线部分嵌入在树脂绝缘层中，并且厚膜布线部分从树脂绝缘层的第一表面突出。 厚膜布线图形的嵌入布线部分的线宽大于精细布线图案的线宽。

公开(公告)号：US09295163B2

公开(公告)日：2016-03-22

申请号：US13906136

申请日：2013-05-30

Applicant: Dyi-Chung Hu

Inventor： Dyi-Chung Hu

IPC: H05K3/24 ,  H05K1/11 ,  H05K3/10

CPC classification number: H05K1/119 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K3/107 ,  H05K3/244 ,  H05K2201/0347 ,  H05K2201/0376 ,  Y02P70/611 ,  Y10T29/49002

Abstract: A formation method of circuit board structure is disclosed. The formation method comprises: forming an intermediate substrate having interconnections therein and circuit patterns on both upper and lower surfaces, wherein the interconnections electrically connect the upper and lower circuit patterns; forming an upper dielectric layer overlying the upper circuit patterns, wherein the upper dielectric layer has a plurality of trenches therein; forming conductive wires in the trenches using e-less plating; and forming at least one protective layer overlying the conductive wires using a surface finishing process. The circuit board structure features formation of embedded conductive wires in the dielectric layer so that a short circuit can be avoid.

Abstract translation: 公开了一种电路板结构的形成方法。 形成方法包括：在其中形成具有互连的中间衬底和上表面和下表面上的电路图案，其中互连电连接上电路图案和下电路图案; 形成覆盖上层电路图案的上介电层，其中上电介质层中具有多个沟槽; 使用无电镀在沟槽中形成导线; 以及使用表面精加工方法形成覆盖在导线上的至少一个保护层。 电路板结构特征在于在电介质层中形成嵌入的导线，从而可以避免短路。

公开(公告)号：US20160079151A1

公开(公告)日：2016-03-17

申请号：US14692769

申请日：2015-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H05K1/18 ,  H05K3/00 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H05K3/32

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

Abstract translation: 本发明提供一种具有嵌入式电子部件的封装结构和制造封装结构的方法。 该方法包括：在载体上形成第一布线层; 移除载体并在键合载体上形成第一布线层; 在第一布线层上设置电子部件; 在所述第一布线层上形成封装层，第二布线层和绝缘层; 在所述电子部件和所述第二布线层上设置芯片; 并形成覆盖芯片的覆盖层。 本发明可以有效地减少包装结构和电子部件的厚度而不使用粘合剂。

公开(公告)号：US09288902B2

公开(公告)日：2016-03-15

申请号：US14097049

申请日：2013-12-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Eun Sil Kim ,  Sung Han Kim ,  Sa Yong Lee ,  Jin Ho Hong ,  Yong Il Kwon ,  Sang Hyun Shin ,  Keun Yong Lee

IPC: H05K1/00 ,  H05K1/03 ,  G03F7/40 ,  H05K3/10 ,  H05K3/12 ,  H05K1/02 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K1/0306 ,  G03F7/40 ,  H05K1/0274 ,  H05K1/0393 ,  H05K3/107 ,  H05K3/1258 ,  H05K3/4061 ,  H05K3/426 ,  H05K2201/0376

Abstract: Disclosed herein are a printed circuit board and a method of manufacturing the same.The printed circuit board includes a light-blocking glass substrate; a negative photosensitive insulating layer formed on the glass substrate; and a circuit pattern formed on the glass substrate and embedded in the negative photosensitive insulating layer.

Abstract translation: 这里公开了一种印刷电路板及其制造方法。 印刷电路板包括遮光玻璃基板; 形成在所述玻璃基板上的负光敏绝缘层; 以及形成在玻璃基板上并嵌入负光敏绝缘层中的电路图案。

公开(公告)号：US20160047766A1

公开(公告)日：2016-02-18

申请号：US14460578

申请日：2014-08-15

Applicant: John Andrew Lebens ,  Ronald Steven Cok ,  Yongcai Wang

Inventor： John Andrew Lebens ,  Ronald Steven Cok ,  Yongcai Wang

IPC: G01N27/12 ,  G01N27/07

CPC classification number: G01N27/126 ,  G01N27/07 ,  G02F1/13439 ,  G06F3/044 ,  G06F2203/04103 ,  H05K3/0014 ,  H05K3/1258 ,  H05K2201/0108 ,  H05K2201/0112 ,  H05K2201/0257 ,  H05K2201/0269 ,  H05K2201/0272 ,  H05K2201/0338 ,  H05K2201/0376 ,  H05K2201/2054 ,  H05K2203/0108 ,  H05K2203/1131 ,  H05K2203/1476

Abstract: An imprinted electronic sensor structure on a substrate for sensing an environmental factor includes a cured layer having a layer surface located on the substrate. Spatially separated micro-channels extend from the layer surface into the cured layer. A multi-layer micro-wire is formed in each micro-channel. Each multi-layer micro-wire includes at least a conductive layer and a reactive layer. The reactive layer is exposed to the environmental factor. The conductive layer is a cured electrical conductor located only within the micro-channel and at least a portion of the reactive layer responds to the environmental factor.

Abstract translation: 用于感测环境因素的基板上的印刷电子传感器结构包括具有位于基板上的层表面的固化层。 空间分离的微通道从层表面延伸到固化层。 在每个微通道中形成多层微线。 每个多层微线包括至少一个导电层和一个反应层。 反应层暴露于环境因素。 导电层是仅位于微通道内的固化电导体，并且反应层的至少一部分响应于环境因素。