公开(公告)号：US20210389769A1

公开(公告)日：2021-12-16

申请号：US16898308

申请日：2020-06-10

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Iuri Frosio ,  Zahra Ghodsi ,  Anima Anandkumar ,  Timothy Tsai ,  Stephen W. Keckler ,  Alejandro Troccoli

IPC: G05D1/02 ,  G01S13/931 ,  G05D1/00 ,  B60W60/00 ,  G05B13/02

Abstract: Techniques to generate driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. Nodes of the path are assigned a time for action to avoid collision from the node. The generated scenarios may be simulated in a computer.

公开(公告)号：US20210387643A1

公开(公告)日：2021-12-16

申请号：US16898379

申请日：2020-06-10

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Iuri Frosio ,  Zahra Ghodsi ,  Anima Anandkumar ,  Timothy Tsai ,  Stephen W. Keckler

IPC: B60W60/00 ,  B60W30/09 ,  B60W30/095

Abstract: Techniques to characterize driving scenarios for autonomous vehicles characterize a path in a driving scenario according to metrics such as narrowness and effort. The scenarios may be characterized using a tree-based or tensor-based approach.

公开(公告)号：US11184008B2

公开(公告)日：2021-11-23

申请号：US16943529

申请日：2020-07-30

Applicant: NVIDIA Corp.

Inventor： Gaurawa Kumar ,  Ky-Anh Tran ,  Olakanmi Oluwole ,  Vishnu Balan

IPC: H03D3/24 ,  H03L7/08 ,  H04L25/497 ,  H04L25/49 ,  H04L25/06 ,  H04L25/03

Abstract: This disclosure relates to a receiver that includes a clock and data recovery loop and a phase offset loop. The clock and data recovery loop may be controlled by a sum of gradients for a plurality of data interleaves. The phase offset loop may be controlled by an accumulated differential gradient for each of the data interleaves.

公开(公告)号：US20210344944A1

公开(公告)日：2021-11-04

申请号：US17368129

申请日：2021-07-06

Applicant: NVIDIA Corp.

Inventor： Johan Pontus Andersson ,  Jim Nilsson ,  Tomas Guy Akenine-Möller

IPC: H04N19/513 ,  H04N19/132 ,  G06T15/06 ,  H04N19/182 ,  H04N19/423

Abstract: A method dynamically selects one of a first sampling order and a second sampling order for a ray trace of pixels in a tile where the selection is based on a motion vector for the tile. The sampling order may be a bowtie pattern or an hourglass pattern.

公开(公告)号：US11144087B2

公开(公告)日：2021-10-12

申请号：US16351319

申请日：2019-03-12

Applicant: NVIDIA Corp.

Inventor： Roger Allen ,  Alan Menezes ,  Tom Ogletree ,  Shounak Kamalapurkar ,  Abhijat Ranade

IPC: G06F1/12 ,  G06F9/48 ,  G06F9/38 ,  H04L12/26 ,  G06F9/30

Abstract: Performance monitors are placed on computational units in different clock domains of an integrated circuit. A central dispatcher generates trigger signals to the performance monitors to cause the performance monitors to respond to the trigger signals with packets reporting local performance counts for the associated computational units. The data in the packets are correlated into a single clock domain. By applying a trigger and reporting system, the disclosed approach can synchronize the performance metrics of the various computational units in the different clock domains without having to route a complex global clock reference signal to all of the performance monitors.

公开(公告)号：US11144080B2

公开(公告)日：2021-10-12

申请号：US16723700

申请日：2019-12-20

Applicant: NVIDIA Corp.

Inventor： Sudhir Kudva ,  John Wilson

IPC: G05F1/42 ,  G05F1/46 ,  G05F1/563 ,  G05F1/565 ,  G05F1/575

Abstract: High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.

公开(公告)号：US11133794B1

公开(公告)日：2021-09-28

申请号：US17020556

申请日：2020-09-14

Applicant: NVIDIA Corp.

Inventor： Stephen G Tell ,  Matthew Rudolph Fojtik ,  John Poulton

IPC: H03K5/14 ,  G04F10/00

Abstract: This disclosure relates to a circuit comprising a first, second, and third data latch, and an input for a data signal. The first data latch may be configured to sample a delayed version of the data signal in response to a first control signal. The second data latch may be configured to sample the delayed version of the data signal in response to a run clock signal. The run clock signal may be configured to run for a predefined number of clock cycles subsequent to the first control signal. The third data latch may be configured to sample either an output signal of the first data latch or an output signal of the second data latch in response to a second control signal received after the predefined number of clock cycles of the run clock signal.

公开(公告)号：US20210124559A1

公开(公告)日：2021-04-29

申请号：US16661888

申请日：2019-10-23

Applicant: NVIDIA Corp.

Inventor： Ilyas Elkin ,  Ge Yang ,  Xi Zhang

IPC: G06F7/509 ,  G06F7/533 ,  G06F7/53

Abstract: This disclosure relates to an adder circuit. The adder circuit comprises an operand input and a second operand input to an XNOR cell. The XNOR cell may be configured to provide the operand input and the second operand input to both a NAND gate and a first OAI cell. A second OAI cell may transform the output of the XNOR cell into a carry out signal.

公开(公告)号：US20210088784A1

公开(公告)日：2021-03-25

申请号：US16578077

申请日：2019-09-20

Applicant: NVIDIA Corp.

Inventor： Eric Whitmire ,  Kaan Aksit ,  Michael Stengel ,  Jan Kautz ,  David Luebke ,  Ben Boudaoud

IPC: G02B27/01 ,  G09F9/33 ,  F21V8/00 ,  G06K9/00 ,  G06F3/01

Abstract: A gaze tracking system for use by the driver of a vehicle includes an opaque frame circumferentially enclosing a transparent field of view of the driver, light emitting diodes coupled to the opaque frame for emitting infrared light onto various regions of the driver's eye gazing through the transparent field of view, and diodes for sensing intensity of infrared light reflected off of various regions of the driver's eye.

公开(公告)号：US20200374594A1

公开(公告)日：2020-11-26

申请号：US16934895

申请日：2020-07-21

Applicant: NVIDIA Corp.

Inventor： Hans Eberle ,  Larry Robert Dennison

IPC: H04N21/472 ,  H04N21/2387 ,  H04N21/6583 ,  H04L12/743 ,  H04N21/43 ,  H04L12/841 ,  H04L12/733 ,  H04N21/234

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.