公开(公告)号：US20100051944A1

公开(公告)日：2010-03-04

申请号：US12545235

申请日：2009-08-21

Applicant: Takahisa Kato ,  Yasuhiro Shimada

Inventor： Takahisa Kato ,  Yasuhiro Shimada

IPC: H01L21/66 ,  H01L21/306 ,  H01L31/0232

CPC classification number: B81C1/00626 ,  B81B2201/0271 ,  B81C1/00404 ,  B81C2201/0133 ,  B81C2201/0198

Abstract: A silicon processing method includes: forming a mask pattern on a principal plane of a single-crystal silicon substrate; and applying crystal anisotropic etching to the principal surface to form a structure including a (111) surface and a crystal surface equivalent thereto and having width W1 and length L1. The principal plane includes a (100) surface and a crystal surface equivalent thereto or a (110) surface and a crystal surface equivalent thereto. A determining section for determining the width W1 of the structure is formed in the mask pattern. The width of the determining section for the width W1 of the mask pattern is width W2. The width of the mask pattern other than the determining section is larger than the width W2 over a length direction of the mask pattern.

Abstract translation: 硅处理方法包括：在单晶硅衬底的主平面上形成掩模图案; 并对主表面施加结晶各向异性蚀刻，形成包括（111）表面和与其等效的晶面的结构，并具有宽度W1和长度L1。 主平面包括（100）表面和与其等效的（110）表面和与其等效的（110）表面和晶体表面。 用于确定结构的宽度W1的确定部分形成在掩模图案中。 掩模图案的宽度W1的确定部的宽度为宽度W2。 除了确定部分之外的掩模图案的宽度大于在掩模图案的长度方向上的宽度W2。

公开(公告)号：US20090236309A1

公开(公告)日：2009-09-24

申请号：US12052956

申请日：2008-03-21

Applicant: Dan B. Millward ,  Timothy Quick

Inventor： Dan B. Millward ,  Timothy Quick

IPC: B44C1/22 ,  B05D5/00

CPC classification number: H01L21/76828 ,  B81C1/00031 ,  B81C2201/013 ,  B81C2201/0149 ,  B81C2201/0198 ,  B82Y30/00 ,  C08F299/02 ,  C08F299/0492 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31133 ,  H01L21/76802 ,  H01L21/76877

Abstract: Methods for fabricating sublithographic, nanoscale microstructures utilizing self-assembling block copolymers, and films and devices formed from these methods are provided.

Abstract translation: 提供了利用自组装嵌段共聚物制造亚光刻，纳米级微结构的方法，以及由这些方法形成的膜和器件。

公开(公告)号：US20080088221A1

公开(公告)日：2008-04-17

申请号：US11730120

申请日：2007-03-29

Applicant: Seok-whan Chung ,  Seok-jin Kang ,  Hyun-koo Jeong

Inventor： Seok-whan Chung ,  Seok-jin Kang ,  Hyun-koo Jeong

IPC: H01J29/80

CPC classification number: B81C1/00396 ,  B81C2201/0198

Abstract: A shadow mask, a method of manufacturing the shadow mask, and a method of forming a thin film using the shadow mask are provided. The shadow mask includes an upper layer and a lower layer. The upper layer includes a first opening. The lower layer is formed on a lower surface of the upper layer around the first opening and includes an opening having the same size as the first opening. When the thin film is formed using the shadow mask, the lower layer of the shadow mask is close to the edge of a cavity of a substrate, and a position on which the thin film may be formed as defined by the lower layer of the shadow mask. Therefore, the thickness of the thin film can be uniform.

Abstract translation: 提供荫罩，荫罩的制造方法以及使用荫罩形成薄膜的方法。 荫罩包括上层和下层。 上层包括第一开口。 下层形成在第一开口周围的上层的下表面上，并且包括具有与第一开口相同尺寸的开口。 当使用荫罩形成薄膜时，荫罩的下层靠近基板的空腔的边缘，并且可以由薄膜的下层限定薄膜的位置 面具。 因此，薄膜的厚度可以是均匀的。

公开(公告)号：US20240192483A1

公开(公告)日：2024-06-13

申请号：US18584740

申请日：2024-02-22

Applicant: Hamamatsu Photonics K.K.

Inventor： Tatsuya SUGIMOTO ,  Tomofumi SUZUKI ,  Kyosuke KOTANI ,  Yutaka KURAMOTO ,  Daiki SUZUKI

IPC: G02B26/08 ,  B81B3/00 ,  B81C1/00 ,  G02B7/182 ,  G02B26/10 ,  H02N1/00

CPC classification number: G02B26/0841 ,  B81B3/0045 ,  B81C1/00555 ,  G02B7/1821 ,  G02B26/105 ,  H02N1/008 ,  B81B2201/042 ,  B81C2201/013 ,  B81C2201/0174 ,  B81C2201/0198

Abstract: An optical device includes a support portion, a movable portion; and a pair of torsion bars. An optical function portion is provided on one surface of the movable portion and a rib portion is provided on the other surface of the movable portion. The rib portion includes eight extending portions of first to eighth extending portions. When setting directions in which the first to eighth extending portions extend as first to eighth extending directions respectively, and setting an angle between the first and second extending directions as a first angle, an angle between the third and fourth extending directions as a second angle, an angle between the fifth and sixth extending directions as a third angle, and an angle between the seventh and eighth extending directions as a fourth angle, each of the first and second angle is larger than each of the third and fourth angle.

公开(公告)号：US20240182298A1

公开(公告)日：2024-06-06

申请号：US18525410

申请日：2023-11-30

Applicant: Robert Bosch GmbH

Inventor： Johannes Classen

IPC: B81C1/00

CPC classification number: B81C1/00619 ,  B81C2201/0116 ,  B81C2201/0132 ,  B81C2201/0198 ,  B81C2203/035 ,  B81C2203/0785

Abstract: A method producing a microelectromechanical component. A dielectric layer is structured on an upper side of a substrate forming a grating, and a blind hole is formed beneath the grating. A cover layer is arranged on the dielectric layer closing the blind hole. A layer sequence is arranged on the cover layer and above the blind hole. Functional structures are formed in the layer sequence and an access channel extending through the layer sequence to the blind hole is formed. A further substrate is connected to the substrate. The functional structures are enclosed in a cavity, connected to the blind hole, between the substrate and the further substrate. Another blind hole is formed on an underside of the substrate. The blind hole is opened in the region of the other blind hole. A cavity internal pressure is set, and the blind hole is closed.

公开(公告)号：US20230219808A1

公开(公告)日：2023-07-13

申请号：US18151631

申请日：2023-01-09

Applicant: Robert Bosch GmbH

Inventor： Andreas Prinzen ,  Christof Schwenk ,  Frank Reichenbach ,  Friedjof Heuck ,  Heiko Stahl ,  Nicolas Schorr

IPC: B81C1/00

CPC classification number: B81C1/00571 ,  B81C2201/0198 ,  B81C2203/0109 ,  B81C2201/0132

Abstract: A method for producing a bonding pad for a micromechanical sensor element. The method includes: depositing a first metal layer onto a top face of the functional layer, and depositing a second metal layer onto the first metal layer, wherein only the first layer or only the second layer is formed in a border region extending around a bonding pad region; covering a protective layer over a top face of the second metal layer in the bonding pad region and over the first or second metal layer in an inner peripheral portion of the border region, which inner peripheral portion adjoins the bonding pad region; etching the first or second layer at least in an outer peripheral portion of the border region down to the top face of the functional layer; removing the protective layer; carrying out an etching process starting from the top face of the layered structure.

公开(公告)号：US09911603B2

公开(公告)日：2018-03-06

申请号：US15397092

申请日：2017-01-03

Applicant: International Business Machines Corporation

Inventor： Joy Cheng ,  Michael A. Guillorn ,  Chi-Chun Liu ,  Hsinyu Tsai

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L21/768 ,  C08L53/00 ,  G03F7/00 ,  G03F1/00

CPC classification number: H01L21/0271 ,  B81C2201/0198 ,  C08L53/00 ,  C08L53/005 ,  G03F1/00 ,  G03F7/0002 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816

Abstract: After forming spacers over a hard mask layer using a sidewall image transfer process, a neutral material layer is formed on the portions of the hard mask layer that are not covered by the spacers. The spacers and the neutral material layer guide the self-assembly of a block copolymer material. The microphase separation of the block copolymer material provides a lamella structure of alternating domains of the block copolymer material.

公开(公告)号：US20170365507A1

公开(公告)日：2017-12-21

申请号：US15630597

申请日：2017-06-22

Applicant: Infineon Technologies AG

Inventor： Alfons Dehe ,  Damian Sojka ,  Andre Schmenn ,  Carsten Ahrens

IPC: H01L21/762 ,  H01L23/60 ,  H01L21/764 ,  H02H9/04 ,  H01L27/02 ,  H01L23/00

CPC classification number: H01L21/76289 ,  B81C1/00119 ,  B81C1/00214 ,  B81C1/00404 ,  B81C1/00484 ,  B81C1/00531 ,  B81C1/00539 ,  B81C1/00571 ,  B81C2201/0111 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/0135 ,  B81C2201/016 ,  B81C2201/0198 ,  B81C2201/053 ,  H01J1/3044 ,  H01J1/308 ,  H01J2201/30411 ,  H01J2201/3048 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/283 ,  H01L21/31058 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/764 ,  H01L23/60 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L27/0288 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H02H9/046 ,  H03K17/545 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment of the present invention, an electronic device includes a first emitter/collector region and a second emitter/collector region disposed in a substrate. The first emitter/collector region has a first edge/tip, and the second emitter/collector region has a second edge/tip. A gap separates the first edge/tip from the second edge/tip. The first emitter/collector region, the second emitter/collector region, and the gap form a field emission device.

公开(公告)号：US09567213B1

公开(公告)日：2017-02-14

申请号：US14827683

申请日：2015-08-17

Applicant: Texas Instruments Incorporated

Inventor： John Charles Ehmke ,  Virgil Cotoco Ararao

IPC: H01L21/00 ,  H01L21/44 ,  H01L21/31 ,  G02B6/12 ,  G02B5/124 ,  G09G3/34 ,  H01J5/00 ,  H01L23/02 ,  B81C1/00 ,  B81B7/00 ,  G02B26/08 ,  G02B6/42 ,  G02B26/00 ,  B82Y30/00

CPC classification number: B81B7/0038 ,  B81B2203/0315 ,  B81C1/00269 ,  B81C1/00285 ,  B81C1/00293 ,  B81C2201/0108 ,  B81C2201/013 ,  B81C2201/0188 ,  B81C2201/0198 ,  B81C2201/053 ,  B81C2203/0109 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/035 ,  B82Y30/00 ,  G02B6/4204 ,  G02B6/4208 ,  G02B6/4248 ,  G02B26/001 ,  G02B26/0833 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/03612 ,  H01L2224/03614 ,  H01L2224/039 ,  H01L2224/04026 ,  H01L2224/05083 ,  H01L2224/05109 ,  H01L2224/05123 ,  H01L2224/05138 ,  H01L2224/05163 ,  H01L2224/05166 ,  H01L2224/0517 ,  H01L2224/05562 ,  H01L2224/27462 ,  H01L2224/2747 ,  H01L2224/279 ,  H01L2224/29006 ,  H01L2224/29011 ,  H01L2224/29023 ,  H01L2224/29109 ,  H01L2224/29144 ,  H01L2224/32058 ,  H01L2224/32227 ,  H01L2224/83121 ,  H01L2224/83193 ,  H01L2224/8381 ,  H01L2224/83825 ,  H01L2224/94 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/1461 ,  H01L2924/164 ,  H01L2924/00014 ,  H01L2924/01049 ,  H01L2224/03 ,  H01L2924/01042 ,  H01L2924/01072 ,  H01L2924/01004 ,  H01L2224/83 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03462

Abstract: A hermetic package comprising a substrate (110) having a surface with a MEMS structure (101) of a first height (101a), the substrate hermetically sealed to a cap (120) forming a cavity over the MEMS structure; the cap attached to the substrate surface by a vertical stack (130) of metal layers adhering to the substrate surface and to the cap, the stack having a continuous outline surrounding the MEMS structure while spaced from the MEMS structure by a distance (140); the stack having a bottom first metal seed film (131a) adhering to the substrate and a bottom second metal seed film (131b) adhering to the bottom first seed film, both seed films of a first width (131c) and a common sidewall (138); further a top first metal seed film (132a) adhering to the cap and a top second metal seed film (132b) adhering to the top first seed film, both seed films with a second width (132c) smaller than the first width and a common sidewall (139); the bottom and top metal seed films tied to a metal layer (135) including gold-indium intermetallic compounds, layer (135) having a second height (133a) greater than the first height and encasing the seed films and common sidewalls.

Abstract translation: 一种密封包装，其包括具有具有第一高度（101a）的MEMS结构（101）的表面的基底（110），所述基底被气密地密封到在所述MEMS结构上形成空腔的帽（120） 所述盖通过粘附到所述基板表面和所述盖的金属层的垂直堆叠（130）附接到所述基板表面，所述堆叠具有围绕所述MEMS结构的连续轮廓，同时与所述MEMS结构隔开距离（140）; 所述堆叠具有附着到所述基板的底部第一金属种子膜（131a）和粘附到所述底部第一种子膜的底部第二金属种子膜（131b），具有第一宽度（131c）和公共侧壁（138）的两种种子膜 ）; 另外，粘附到盖的顶部第一金属种子膜（132a）和粘附到顶部第一种子膜的顶部第二金属种子膜（132b），具有小于第一宽度的第二宽度（132c）的两种种子膜和共同的 侧壁（139）; 连接到包括金 - 铟金属间化合物的金属层（135）的底部和顶部金属种子膜，具有大于第一高度的第二高度（133a）的层（135）并且包围种子膜和共同侧壁。

公开(公告)号：US09434609B2

公开(公告)日：2016-09-06

申请号：US13629908

申请日：2012-09-28

Applicant: JSR CORPORATION

Inventor： Satoshi Dei ,  Takashi Mori ,  Kazunori Takanashi

IPC: B81C1/00 ,  C08G77/388 ,  G03F7/075 ,  G03F7/004 ,  G03F7/09 ,  G03F7/11 ,  H05K3/06 ,  C08G77/14 ,  C08G77/24 ,  C09D183/08

CPC classification number: B81C1/00396 ,  B81C1/00388 ,  B81C2201/0198 ,  C08G77/14 ,  C08G77/24 ,  C08G77/388 ,  C09D183/08 ,  G03F7/0046 ,  G03F7/0752 ,  G03F7/0757 ,  G03F7/094 ,  G03F7/11 ,  H05K3/061 ,  H05K2203/05

Abstract: A pattern-forming method in which processibility of a silicon-containing film in etching with a fluorine gas and resistance against etching with an oxygen gas can be together improved in a multilayer resist process to form a finer pattern. Provided is a pattern-forming method that includes the steps of (1) providing a silicon-containing film on the upper face side of a substrate to be processed using a polysiloxane composition; (2) forming a resist pattern on the silicon-containing film; (3) dry-etching the silicon-containing film using the resist pattern as a mask to form a silicon-containing pattern; and (4) dry-etching the substrate to be processed using the silicon-containing pattern as a mask to form a pattern, in which the polysiloxane composition includes (A) a polysiloxane containing a fluorine atom, and (B) a crosslinking accelerator.

Abstract translation: 在多层抗蚀剂工艺中，可以在多层抗蚀剂工艺中一起改进其中利用氟气蚀刻含硅膜和耐氧蚀性的可加工性的图案形成方法，以形成更精细的图案。 提供了一种图案形成方法，其包括以下步骤：（1）使用聚硅氧烷组合物在待处理基板的上表面上提供含硅膜; （2）在含硅膜上形成抗蚀剂图案; （3）使用抗蚀剂图案作为掩模对含硅膜进行干蚀刻以形成含硅图案; 和（4）使用含硅图案作为掩模对待处理的基板进行干蚀刻以形成其中聚硅氧烷组合物包含（A）含氟原子的聚硅氧烷和（B）交联促进剂的图案。