公开(公告)号：US20170347453A1

公开(公告)日：2017-11-30

申请号：US15336904

申请日：2016-10-28

Applicant: FUJI XEROX CO., LTD.

Inventor： Shigemi OHTSU

IPC: H05K1/14 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/144 ,  H05K1/028 ,  H05K1/111 ,  H05K1/117 ,  H05K3/243 ,  H05K3/363 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/09172 ,  H05K2201/09781 ,  H05K2201/10977

Abstract: Provided is a wiring board including a substrate formed of an insulation material, and plural conductive patterns including plural electrodes arranged on a surface of the substrate along an end surface of the substrate, and plural wiring patterns connected to the plural electrodes, respectively, wherein the substrate includes a notch formed between electrode groups each of which includes a predetermined number of the electrodes.

公开(公告)号：US20170339784A1

公开(公告)日：2017-11-23

申请号：US15534897

申请日：2015-12-10

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Andreas Zluc ,  Gerald Weidinger ,  Mario Schober ,  Hannes Stahr ,  Timo Schwarz ,  Benjamin Gruber

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/14 ,  H01L23/00 ,  H05K3/46 ,  H05K3/00 ,  H05K1/18 ,  H05K1/03 ,  H05K1/11 ,  H01L23/538

CPC classification number: H05K1/0271 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/145 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2924/0002 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/0353 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/185 ,  H05K1/189 ,  H05K3/0017 ,  H05K3/0097 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09136 ,  H01L2924/00

Abstract: A circuit board is described which includes a layer composite with at least one dielectric layer which includes a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis perpendicular thereto, and which includes a layer thickness along a z-axis which is perpendicular with respect to the x-axis and to the y-axis; and at least one metallic layer which is attached to the dielectric layer in a planar manner. The layer composite along the z-axis is free from a symmetry plane which is oriented in parallel with respect to the xy-plane, and the dielectric layer includes a dielectric material which has an elastic modulus E in a range between 1 and 20 GPa and along the x-axis and along the y-axis a coefficient of thermal expansion in a range between 0 and 17 ppm/K. A method of manufacturing such a circuit board is also described. Further, a method of manufacturing a circuit board structure comprising two asymmetric circuit boards and a method of manufacturing two processed asymmetric circuit boards from a larger circuit board structure is described.

公开(公告)号：US20170339783A1

公开(公告)日：2017-11-23

申请号：US15534172

申请日：2015-12-10

Applicant: AT & S Austria Technologie & Systemtechnik Aktiengesellschaft

Inventor： Hannes Stahr ,  Andreas Zluc ,  Timo Schwarz ,  Gerald Weidinger

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/14 ,  H01L23/00 ,  H05K3/46 ,  H05K3/00 ,  H05K1/18 ,  H05K1/03 ,  H05K1/11 ,  H01L23/538

CPC classification number: H05K1/0271 ,  H01L21/481 ,  H01L21/4857 ,  H01L21/568 ,  H01L23/145 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5387 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/32145 ,  H01L2224/73267 ,  H01L2924/0002 ,  H01L2924/18162 ,  H01L2924/19105 ,  H01L2924/3511 ,  H05K1/0353 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/185 ,  H05K1/189 ,  H05K3/0017 ,  H05K3/0097 ,  H05K3/4602 ,  H05K2201/0129 ,  H05K2201/0133 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/068 ,  H05K2201/09136 ,  H01L2924/00

Abstract: A circuit board and a method of manufacturing a circuit board or two circuit boards are illustrated and described. The circuit board includes (a) a dielectric layer with a planar extension in parallel with respect to an xy-plane which is spanned by an x-axis and a y-axis perpendicular thereto and a layer thickness along a z-direction which is perpendicular with respect to the x-axis and to the y-axis; (b) a metallic layer which is attached to the dielectric layer in a planar manner; and (c) a component which is embedded in the dielectric layer and/or in a dielectric core-layer of the circuit board. The dielectric layer includes a dielectric material which has (i) an elastic modulus E in a range between 1 and 20 GPa and (ii) a coefficient of thermal expansion in a range between 0 and 17 ppm/K along the x-axis and along the y-axis.

公开(公告)号：US20170330818A1

公开(公告)日：2017-11-16

申请号：US15527740

申请日：2015-12-11

Applicant: DENSO CORPORATION

Inventor： Tetsuto YAMAGISHI ,  Toshihiro NAGAYA ,  Masayuki TAKENAKA ,  Shinji HIRAMITSU

IPC: H01L23/40 ,  H01L23/28 ,  H01L23/367 ,  H05K1/02

CPC classification number: H01L23/40 ,  H01L23/145 ,  H01L23/28 ,  H01L23/29 ,  H01L23/3121 ,  H01L23/367 ,  H01L23/3737 ,  H01L23/4006 ,  H01L23/42 ,  H01L2023/405 ,  H01L2924/0002 ,  H05K1/0209 ,  H05K3/284 ,  H05K2201/062 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/10166 ,  H05K2201/10409 ,  H01L2924/00

Abstract: An electronic device includes: a resin substrate that includes insulation resin on which wiring made of conductive material is provided; a heat-generation element that is a circuit element mounted on a first surface of the resin substrate, and is operated to generate heat; and a sealing resin that is provided on the first surface, and seals the heat-generation element. An opposite surface of the sealing resin opposite to a surface of the sealing resin in contact with the first surface is thermally connected to a heat radiation member and mounted on the heat radiation member. Each of the resin substrate and the sealing resin has a bend shape convex toward the opposite surface when each of surrounding temperatures is a normal temperature and has a linear expansion coefficient for maintaining a bend shape convex toward the opposite surface when each of the surrounding temperatures is a high temperature.

公开(公告)号：US20170327683A1

公开(公告)日：2017-11-16

申请号：US15258722

申请日：2016-09-07

Applicant: Elite Electronic Material (Zhongzhan) Co., Ltd.

Inventor： Zhilong HU ,  Xiang XIONG ,  Xingfa CHEN

IPC: C08L63/00 ,  C08J5/24 ,  H05K1/03 ,  C08L63/04

CPC classification number: C08L63/00 ,  C08J5/24 ,  C08J2363/00 ,  C08J2363/04 ,  C08J2425/08 ,  C08J2463/10 ,  C08J2479/04 ,  C08L63/04 ,  C08L2203/20 ,  C08L2205/035 ,  H05K1/0353 ,  H05K2201/068

Abstract: Provided is a resin composition, comprising epoxy resin, oxydianiline type benzoxazine resin, styrene-maleic anhydride resin and tetra-phenol resin. The resin composition may be baked for producing products such as prepregs, resin films, resin-coated coppers, laminates and printed circuit boards, which satisfy one or more or all of desirable properties such as higher dimensional stability after a reflow process, better thermal resistance after horizontal black oxide process, low dielectric constant, low dissipation factor, high thermal resistance and flame retardancy.

公开(公告)号：US20170280559A1

公开(公告)日：2017-09-28

申请号：US15468697

申请日：2017-03-24

Applicant: HITACHI METALS, LTD.

Inventor： Hirokazu NAKAJIMA ,  Kohei SAKAGUCHI

IPC: H05K1/03 ,  C04B37/00 ,  B28B11/24 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/0306 ,  B28B11/243 ,  B32B18/00 ,  C04B35/111 ,  C04B35/195 ,  C04B35/62615 ,  C04B35/62625 ,  C04B35/6263 ,  C04B35/6264 ,  C04B35/62655 ,  C04B35/62675 ,  C04B35/63416 ,  C04B35/6342 ,  C04B35/638 ,  C04B37/001 ,  C04B2235/3201 ,  C04B2235/3213 ,  C04B2235/3236 ,  C04B2235/3244 ,  C04B2235/3262 ,  C04B2235/3263 ,  C04B2235/3267 ,  C04B2235/3281 ,  C04B2235/3298 ,  C04B2235/3409 ,  C04B2235/3445 ,  C04B2235/36 ,  C04B2235/442 ,  C04B2235/5409 ,  C04B2235/5436 ,  C04B2235/602 ,  C04B2235/604 ,  C04B2235/6562 ,  C04B2235/9607 ,  C04B2237/341 ,  C04B2237/343 ,  C04B2237/704 ,  H05K1/024 ,  H05K1/0271 ,  H05K1/162 ,  H05K1/165 ,  H05K3/4629 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2203/06

Abstract: A ceramic substrate and a method for production thereof are provided, in which the ceramic substrate includes a composite of : a first ceramic layer including Sr anorthite and Al2O3 or an oxide dielectric with a dielectric constant higher than that of Al2O3; and a second ceramic layer including Sr anorthite and cordierite and having a dielectric constant lower than that of the first ceramic layer.

公开(公告)号：US20170273177A1

公开(公告)日：2017-09-21

申请号：US15418991

申请日：2017-01-30

Applicant: Japan Display Inc.

Inventor： Yuuki NISHIMOTO

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K1/0281 ,  H05K1/0271 ,  H05K1/115 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/0154 ,  H05K2201/068 ,  H05K2201/10128 ,  H05K2201/10681

Abstract: A flexible circuit board includes a base material including a first surface and a second surface opposite the first surface, the base material including a conductor layer, a first insulating film covering the first surface of the base material and formed with a first opening, a first insulating member formed inside the first opening and formed with a connection port to expose the conductor layer, the first insulating member having a thermal expansion coefficient smaller than that of the first insulating film, a second insulating film covering the second surface of the base material and formed with a second opening overlapping at least a portion of the first opening in a plan view, and a second insulating member formed inside the second opening and having a thermal expansion coefficient smaller than that of the first insulating film.

公开(公告)号：US09743510B2

公开(公告)日：2017-08-22

申请号：US14579108

申请日：2014-12-22

Applicant: NIKON CORPORATION

Inventor： Ryoichi Suganuma ,  Hirofumi Arima ,  Satoru Suzuki ,  Takuya Sato

IPC: H01L29/16 ,  H05K1/02 ,  H04N5/225 ,  H05K1/05 ,  H05K3/46 ,  H01L27/146 ,  H05K1/11 ,  H05K1/18 ,  H05K3/44 ,  H05K1/03

CPC classification number: H05K1/0271 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15153 ,  H01L2924/1531 ,  H01L2924/16195 ,  H04N5/2253 ,  H05K1/0206 ,  H05K1/0283 ,  H05K1/0366 ,  H05K1/05 ,  H05K1/056 ,  H05K1/111 ,  H05K1/181 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/10015 ,  H05K2201/10121 ,  H01L2924/00014

Abstract: A substrate comprises: a first insulating layer; a second insulating layer having an elastic modulus that is different from an elastic modulus of the first insulating layer; and a core layer that is sandwiched by the first insulating layer and the second insulating layer, and is more rigid than the first insulating layer and the second insulating layer.

公开(公告)号：US09693469B2

公开(公告)日：2017-06-27

申请号：US14134661

申请日：2013-12-19

Applicant: The Charles Stark Draper Laboratory, Inc.

Inventor： Gary B. Tepolt ,  John Merullo ,  Jeffrey C. Thompson ,  Berj Nercessian

IPC: H05K7/00 ,  H05K3/46 ,  H05K1/02 ,  H05K3/28 ,  H05K1/18 ,  H05K3/40

CPC classification number: H05K3/4697 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15153 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K1/0271 ,  H05K1/183 ,  H05K3/284 ,  H05K3/4046 ,  H05K3/4694 ,  H05K2201/068 ,  H05K2203/1572 ,  Y10T156/1064

Abstract: An electronic module subassembly including a substrate. The substrate includes a bottom laminate, a middle laminate coupled to the bottom laminate, and a top laminate coupled to the middle laminate. The middle laminate has a plurality of web areas, each web area defining at least one hole. The defines a planar top surface and a plurality of open areas corresponding to and aligned with the plurality of web areas. First components have a first thickness. At least one first component is in each of the open areas. Second components have a second thickness relatively larger than the first thickness. At least one second component is in each of the open areas. The second components extend into the respective at least one hole of the web areas. Encapsulant fills in the open areas and the web areas.

公开(公告)号：US20170150596A1

公开(公告)日：2017-05-25

申请号：US14947574

申请日：2015-11-20

Applicant: Raytheon Company

Inventor： Tse E. Wong ,  Shea Chen ,  Hoyoung C. Choe

IPC: H05K1/02 ,  H05K1/11 ,  H01L25/065 ,  H01L23/492 ,  H01L23/498

CPC classification number: H05K1/0271 ,  H01L23/4924 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L25/065 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/0305 ,  H05K2201/049 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/094 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2203/047 ,  Y02P70/613

Abstract: A stress reduction interposer is provided for disposition between first and second solder materials of first and second electronic devices, respectively. The stress reduction interposer includes a plate element having a central portion and a periphery surrounding the central portion and being formed to define first cavities having an upper area limit at the periphery and a second cavity having a lower area limit, which is higher than the upper area limit, at the central portion and third and fourth solder materials being disposable in the second cavity and in the first cavities, respectively, to be electrically communicative with the first and second solder materials. The third solder material is more compliant and has a higher melting temperature than at least the second and fourth solder materials.