公开(公告)号：US09140735B2

公开(公告)日：2015-09-22

申请号：US13886285

申请日：2013-05-03

Applicant: Infineon Technologies AG

Inventor： Martin Gruber ,  Angela Kessler

IPC: G01R27/08 ,  G01R27/14 ,  G01R31/26 ,  G01R15/18 ,  G01R31/28 ,  G01R3/00 ,  G01R1/20 ,  H05K1/16 ,  G01R13/34 ,  H05K3/06

CPC classification number: G01R27/14 ,  G01R1/203 ,  G01R3/00 ,  G01R13/347 ,  G01R15/181 ,  G01R31/2648 ,  G01R31/2884 ,  H05K1/0268 ,  H05K1/167 ,  H05K3/06 ,  H05K2201/09736 ,  H05K2201/10166 ,  H05K2203/092 ,  H05K2203/171

Abstract: A method of manufacturing an electronic circuit with an integrally formed capability of providing information indicative of a value of a current flowing in the electronic circuit, wherein the method comprises forming an electrically conductive wiring structure on a substrate, configuring a first section of the wiring structure for contributing to a predefined use function of the electronic circuit, and configuring a second section of the wiring structure for providing information indicative of the value of the current flowing in the electronic circuit upon applying a stimulus signal to the second section, wherein at least a part of the configuring of the first section and the configuring of the second section is performed simultaneously.

Abstract translation: 一种制造电子电路的方法，所述电子电路具有提供表示在所述电子电路中流动的电流的值的信息的整合能力，其中所述方法包括在基板上形成导电布线结构，构成所述布线结构的第一部分 用于对所述电子电路的预定义使用功能作出贡献，以及配置所述布线结构的第二部分，用于在向所述第二部分施加刺激信号时提供指示在所述电子电路中流动的电流的值的信息，其中至少一个 同时执行部分第一部分的配置和第二部分的配置。

公开(公告)号：US20150260382A1

公开(公告)日：2015-09-17

申请号：US14490466

申请日：2014-09-18

Applicant: Toshiba Lighting & Technology Corporation

Inventor： Kiyokazu Hino

IPC: F21V23/00 ,  H05K1/18 ,  H05K3/12 ,  H05K1/11 ,  H05K1/09 ,  H05K1/02 ,  F21V23/06 ,  H05K1/03

CPC classification number: F21V23/001 ,  F21V23/005 ,  F21V23/06 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/09 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K3/1216 ,  H05K3/246 ,  H05K2201/0338 ,  H05K2201/035 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2201/10106 ,  Y02P70/611

Abstract: According to one embodiment, a light emitting module substrate includes: a base body that uses a ceramic; and a wiring pattern which is provided on a surface of the base body and in which a thickness in a region to be soldered is thicker than that in a region other than the region to be soldered.

Abstract translation: 根据一个实施例，发光模块基板包括：使用陶瓷的基体; 以及布置图案，其设置在基体的表面上，并且其中要焊接的区域中的厚度比除了要焊接的区域之外的区域的厚度厚。

公开(公告)号：US20150237717A1

公开(公告)日：2015-08-20

申请号：US14453977

申请日：2014-08-07

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chang-fu Lin Chang ,  Chin-Tsai Yao ,  Ming-Chin Chuang ,  Ko-Cheng Liu ,  Fu-Tang Huang

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K3/4644 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/181 ,  H05K1/02 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/0191 ,  H05K2201/09736 ,  H05K2201/20 ,  H05K2203/0353 ,  H05K2203/0369 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A package substrate is provided, which includes a plurality of dielectric layers and a plurality of circuit layers alternately stacked with the dielectric layers. At least two of the circuit layers have a difference in thickness so as to prevent warpage of the substrate.

Abstract translation: 提供一种封装基板，其包括多个电介质层和与电介质层交替堆叠的多个电路层。 至少两个电路层的厚度不同，以防止基板翘曲。

公开(公告)号：US20150156868A1

公开(公告)日：2015-06-04

申请号：US14611513

申请日：2015-02-02

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masato NOMIYA

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/12 ,  H05K1/03

CPC classification number: H05K1/0298 ,  H01G4/012 ,  H01G4/12 ,  H01G4/30 ,  H05K1/0237 ,  H05K1/025 ,  H05K1/0306 ,  H05K1/092 ,  H05K1/162 ,  H05K3/0067 ,  H05K3/12 ,  H05K3/4629 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/09336 ,  H05K2201/09736

Abstract: The electronic component of this invention includes a multilayer ceramic substrate 14 composed of a plurality of ceramic layers 12. A wiring electrode 16 and a planar electrode 18 are formed on a ceramic layer 12, which is an insulating layer. The planar electrode 18 is formed so as to be spaced apart from the wiring electrode 16 at the certain interval. An edge portion 22 is formed in a region of the planar electrode 18 adjacent to and spaced apart from the wiring electrode 16 at a certain interval. A central portion 20 is formed in a region of the planar electrode 18 other than the edge portion 22. At least the composition of the central portion 20 is different from the composition of the wiring electrode 16, and the composition of the edge portion 22 is the same as the composition of the wiring electrode 16.

Abstract translation: 本发明的电子部件包括由多个陶瓷层12构成的多层陶瓷基板14.在作为绝缘层的陶瓷层12上形成有布线电极16和平面电极18。 平面电极18形成为以一定间隔与布线电极16间隔开。 边缘部分22以一定间隔形成在平面电极18的与布线电极16相邻并间隔开的区域中。 中心部分20形成在平面电极18的除了边缘部分22的区域中。至少中心部分20的组成与布线电极16的组成不同，边缘部分22的组成是 与布线电极16的组成相同。

公开(公告)号：US20150136459A1

公开(公告)日：2015-05-21

申请号：US14549951

申请日：2014-11-21

Applicant: IBIDEN Co., Ltd.

Inventor： Masatoshi KUNIEDA ,  Makoto Terui ,  Ryoujiro Tominaga ,  Takashi Kariya

IPC: H05K1/02 ,  H05K3/40 ,  H05K1/11 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K3/4682 ,  H01L2224/16227 ,  H05K1/0256 ,  H05K1/0265 ,  H05K1/09 ,  H05K1/112 ,  H05K1/113 ,  H05K1/114 ,  H05K1/185 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/0352 ,  H05K2201/0391 ,  H05K2201/0761 ,  H05K2201/0769 ,  H05K2201/094 ,  H05K2201/09736 ,  H05K2201/0989 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/1394 ,  Y02P70/611 ,  Y10T29/49155

Abstract: A wiring board includes a first resin insulating layer, conductor pads on the first insulating layer including first and second conductor pads, a second resin insulating layer on the first insulating layer covering the first and second pads, an outermost conductor layer on the second insulating layer including first and second outermost wiring layers, via conductors through the second insulating layer including a first via conductor connecting the first wiring layer and first pad and a second via conductor connecting the second wiring layer and second pad, and a solder resist layer on the second insulating layer such that the solder resist layer is covering the first wiring layer and has one or more openings exposing the second wiring layer. The first wiring layer includes first main metal, and the second wiring layer includes second main metal which is different from the first metal of the first wiring layer.

Abstract translation: 布线基板包括第一树脂绝缘层，第一绝缘层上包括第一和第二导体焊盘的导体焊盘，覆盖第一和第二焊盘的第一绝缘层上的第二树脂绝缘层，第二绝缘层上的最外层导体层 包括第一和第二最外面布线层，通过第二绝缘层的通孔导体包括连接第一布线层和第一焊盘的第一通孔导体和连接第二布线层和第二焊盘的第二通孔导体，以及在第二绝缘层上的阻焊层 绝缘层，使得阻焊层覆盖第一布线层并且具有暴露第二布线层的一个或多个开口。 第一布线层包括第一主金属，第二布线层包括与第一布线层的第一金属不同的第二主金属。

公开(公告)号：US09006581B2

公开(公告)日：2015-04-14

申请号：US13639640

申请日：2011-04-11

Applicant: Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga ,  Hiroyuki Yasuda

Inventor： Toshiyuki Kawaguchi ,  Kazutoki Tahara ,  Tsutomu Saga ,  Hiroyuki Yasuda

IPC: H05K1/03 ,  H05K1/00 ,  H05K1/09 ,  H05K9/00 ,  H05K1/02

CPC classification number: H05K1/0218 ,  H05K1/0234 ,  H05K1/0242 ,  H05K1/0393 ,  H05K2201/0133 ,  H05K2201/0715 ,  H05K2201/09736

Abstract: A printed wiring board, including a printed wiring member which respectively has object conductor that is subjected to electromagnetic wave shielding on at least one surface of an insulating layer; and an electromagnetic wave shielding member which has an electromagnetic wave shielding layer composed of a low-resistance section and a high-resistance section on at least one surface of a base film. The printed wiring member and the electromagnetic wave shielding member are bonded together with interposition of insulating adhesive layers, and with arrangement of the electromagnetic wave shielding layer separately and in opposition so that the object conductor is covered. The electromagnetic wave shielding layer and the object conductor are composed of the same type of conductive material, and the electromagnetic wave shielding layer is not exposed at the circumferential end faces of the printed wiring board.

Abstract translation: 一种印刷线路板，包括分别具有在绝缘层的至少一个表面上进行电磁波屏蔽的物体导体的印刷布线构件; 以及电磁波屏蔽构件，其在基膜的至少一个表面上具有由低电阻部分和高电阻部分构成的电磁波屏蔽层。 印刷线路构件和电磁波屏蔽构件通过插入绝缘粘合剂层而被接合在一起，并且电磁波屏蔽层的布置分开地和相对地布置，使得物体导体被覆盖。 电磁波屏蔽层和物体导体由相同类型的导电材料构成，并且电磁波屏蔽层不在印刷线路板的周向端面处露出。

公开(公告)号：US20140368963A1

公开(公告)日：2014-12-18

申请号：US14374047

申请日：2013-01-22

Applicant: TDK CORPORATION

Inventor： Shingo Suzuki ,  Kensaku Asakura ,  Takahiro Fujimori

IPC: H05F3/04

CPC classification number: H05F3/04 ,  H01T4/08 ,  H01T4/10 ,  H05K1/026 ,  H05K2201/0175 ,  H05K2201/0272 ,  H05K2201/09736 ,  H05K2201/10196 ,  H05K2203/107

Abstract: An ESD countermeasure device is provided with (i) discharge electrodes that are positioned between first and second insulating substrates and are opposite to each other with a gap therebetween; and (ii) a discharge inducing portion that is disposed at opposing portions of the discharge electrodes and between the opposing portions, wherein a cross-sectional area of each of the opposing portions of the discharge electrodes that are opposite to each other is larger than that of each of lead portions of the discharge electrodes that are opposite to each other.

Abstract translation: ESD对策装置具备：（i）放电位于第一绝缘基板和第二绝缘基板之间并且彼此相对的电极，其间具有间隙; 和（ii）设置在放电电极的相对部分和相对部分之间的放电诱导部分，其中放电电极的彼此相对的每个相对部分的横截面面积大于 的放电电极的引线部分彼此相对。

公开(公告)号：US20140367154A1

公开(公告)日：2014-12-18

申请号：US14300797

申请日：2014-06-10

Applicant: Toyota Jidosha Kabushiki Kaisha

Inventor： Jun Muto

IPC: H05K1/18 ,  H05K3/30 ,  H05K1/02

CPC classification number: H05K1/181 ,  H05K1/0296 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/162 ,  H05K1/165 ,  H05K3/247 ,  H05K2201/0305 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/0979 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2203/043 ,  Y02P70/611 ,  Y10T29/43

Abstract: A capacitor arrangement structure includes: a first wiring pattern; a second wiring pattern; a first electrode pattern that protrudes from the first wiring pattern toward the second wiring pattern; a second electrode pattern that protrudes from the second wiring pattern toward the first wiring pattern so as to run in parallel to the first electrode pattern; and a plurality of capacitors that are arranged in parallel between the first electrode pattern and the second electrode pattern.

Abstract translation: 电容器配置结构包括：第一布线图案; 第二布线图案; 从所述第一布线图案朝向所述第二布线图案突出的第一电极图案; 第二电极图案，其从所述第二布线图案朝向所述第一布线图案突出以与所述第一电极图案平行; 以及平行布置在第一电极图案和第二电极图案之间的多个电容器。

公开(公告)号：US20140251660A1

公开(公告)日：2014-09-11

申请号：US13784866

申请日：2013-03-05

Applicant: Ronald Steven Cok

Inventor： Ronald Steven Cok

IPC: H05K1/02

CPC classification number: H05K3/1258 ,  H05K1/097 ,  H05K2201/0108 ,  H05K2201/09036 ,  H05K2201/09736

Abstract: A variable-depth micro-channel structure includes a substrate. A cured layer is formed on the substrate. A micro-channel embossed in the cured layer has a bottom surface defining two or more different micro-channel depths of the micro-channel. A cured electrical conductor forms a micro-wire in the micro-channel over the bottom surface of the micro-channel and extends across at least a portion of the bottom surface of the micro-channel.

Abstract translation: 可变深度微通道结构包括基底。 在基板上形成固化层。 在固化层中压印的微通道具有限定微通道的两个或多个不同微通道深度的底表面。 固化的电导体在微通道的底表面上的微通道中形成微线，并延伸穿过微通道的底表面的至少一部分。

公开(公告)号：US20140160707A1

公开(公告)日：2014-06-12

申请号：US13707113

申请日：2012-12-06

Applicant: Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

Inventor： Zhichao Zhang ,  Tao Wu ,  Zhiguo Qian ,  Kemal Aygun

IPC: H05K1/18 ,  H05K3/10 ,  H05K1/02

CPC classification number: H05K1/0298 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads to be coupled to a semiconductor die, with a first trace coupled to a first pad among the pads, and a second trace coupled to a second pad among the pads. The first and second traces may have different thicknesses. Other embodiments including additional apparatuses and methods are described.

Abstract translation: 本文描述的一些实施例包括形成这种装置的装置和方法。 一个这样的实施例可以包括具有要耦合到半导体管芯的焊盘的布线布置，其中第一迹线耦合到焊盘之间的第一焊盘，以及耦合到焊盘之间的第二焊盘的第二迹线。 第一和第二迹线可以具有不同的厚度。 描述包括附加装置和方法的其他实施例。