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    Packages for stacked integrated circuit chip cubes
    31.
    发明授权
    Packages for stacked integrated circuit chip cubes 失效
    堆叠集成电路芯片立方体的封装

    公开(公告)号：US5343366A

    公开(公告)日：1994-08-30

    申请号：US903838

    申请日：1992-06-24

    Applicant: Thomas M. Cipolla ,  Paul W. Coteus ,  Ioannis Damianakis ,  Glen W. Johnson ,  Peter G. Ledermann ,  Linda C. Matthew ,  Lawrence S. Mok

    Inventor： Thomas M. Cipolla ,  Paul W. Coteus ,  Ioannis Damianakis ,  Glen W. Johnson ,  Peter G. Ledermann ,  Linda C. Matthew ,  Lawrence S. Mok

    IPC: H01L25/18 ,  H01L25/065 ,  H01L25/07 ,  H05K1/14 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H01R23/68

    CPC classification number: H05K3/363 ,  H01L24/01 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2225/06551 ,  H01L2225/06596 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K2201/0397 ,  H05K2201/048 ,  H05K2201/09172 ,  H05K2201/09909 ,  H05K2201/10484 ,  H05K2201/1059 ,  H05K2201/10681 ,  H05K2201/10984 ,  H05K3/326 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/366 ,  H05K3/4007 ,  H05K3/4092

    Abstract: This invention relates to three dimensional packaging of integrated circuit chips into stacks to form cuboid structures. Between adjacent chips in the stack, there is disposed an electrical interconnection means which is a first substrate having a plurality of conductors one end of which is electrically connected to chip contact locations and the other end of which extends to one side of the chip stack to form a plurality of pin-like electrical interconnection assemblies. The pin-like structures can be formed from projections of the first substrate having an electrical conductor on at least one side thereof extending from this side. Alternatively, the pin-like structures can be formed from conductors which cantilever from both sides of an edge of the first substrate and within which corresponding conductors from both sides are aligned and spaced apart by the first substrate thickness. The spaces contain solder and form solder loaded pin-like structures. The pin-like structures can be directly solder bonded to conductors on a second substrate surface or the pin-like structures can be adapted for insertion into apertures in a second substrate. The second substrate provides a means for electrically inter-connecting a plurality of these cuboids. Preferably, the first and second substrates are circuitized flexible polymeric films. The second substrate is disposed on a third substrate, such as a PC board, with a resilient material therebetween which permits a heat sink to be pressed into intimate contact with an opposite side of the cuboid structures.

    Abstract translation: 本发明涉及将集成电路芯片三维封装成堆栈以形成立方体结构。 在堆叠中的相邻芯片之间，设置有电互连装置，其是具有多个导体的第一基板，其多个导体电连接到芯片接触位置，并且其另一端延伸到芯片堆叠的一侧， 形成多个针状电互连组件。 销状结构可以由在其至少一侧上具有电导体的第一基板的凸起从该侧延伸形成。 或者，销状结构可以由从第一基板的边缘的两侧悬臂的导体形成，并且其中来自两侧的相应导体对准并且间隔开第一基板厚度。 这些空间包含焊料并形成焊料加载的针状结构。 销状结构可以直接焊接到第二衬底表面上的导体上，或者针状结构可以适于插入到第二衬底中的孔中。 第二基板提供用于电连接多个这些长方体的装置。 优选地，第一和第二基底是电路化柔性聚合物膜。 第二基板设置在诸如PC板的第三基板上，其间具有弹性材料，其允许将散热器压紧成与长方体结构的相对侧紧密接触。

    Method of manufacturing double-sided wiring substrate
    33.
    发明授权
    Method of manufacturing double-sided wiring substrate 失效
    制造双面布线基板的方法

    公开(公告)号：US5049244A

    公开(公告)日：1991-09-17

    申请号：US464412

    申请日：1990-01-12

    Applicant: Yoshio Yarita ,  Yoshihiro Kawamura

    Inventor： Yoshio Yarita ,  Yoshihiro Kawamura

    IPC: H05K1/00 ,  H05K3/10 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42

    CPC classification number: H05K3/4076 ,  H05K3/108 ,  H05K3/403 ,  H05K3/426 ,  H05K1/0393 ,  H05K2201/0317 ,  H05K2201/09172 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/0221 ,  H05K3/388

    Abstract: Disclosed is a method of manufacturing a double-sided wiring substrate wherein fine wiring patterns having a low resistivity are formed on both surfaces of a substrate. An insulating substrate having upper, lower, and side surfaces is prepared. The inner wall of a through hole formed in the insulating substrate or a side edge portion of the substrate is used as the side surface. A thin metal film is formed on the entire surface of the insulating substrate including its side surface by a deposition. The insulating film is covered with a resist film except for a wiring pattern region to be formed, and plating is performed. When the resist film is removed, the thin metal film is exposed outside the wiring patterns formed by the thick metal film. Etching is performed for a short period of time to remove a surface layer of the thick metal film and exposed region of the thin metal film.

    Abstract translation: 公开了一种制造双面布线基板的方法，其中在基板的两个表面上形成具有低电阻率的精细布线图案。 制备具有上表面，下表面和侧表面的绝缘基底。 在绝缘基板上形成的通孔的内壁或基板的侧边缘部分被用作侧面。 通过沉积在包括其侧表面的绝缘基板的整个表面上形成薄金属膜。 除了要形成的布线图案区域之外，绝缘膜被抗蚀剂膜覆盖，并进行电镀。 当去除抗蚀剂膜时，薄金属膜暴露在由厚金属膜形成的布线图案的外部。 进行蚀刻短时间以去除厚金属膜的表面层和金属薄膜的暴露区域。

    Method of manufacturing an electrical circuit system and electrical circuit system
    34.
    发明授权
    Method of manufacturing an electrical circuit system and electrical circuit system 失效
    制造电路系统和电路系统的方法

    公开(公告)号：US5042971A

    公开(公告)日：1991-08-27

    申请号：US510465

    申请日：1990-04-16

    Applicant: Stephen D. Ambrose

    Inventor： Stephen D. Ambrose

    IPC: H01R4/04 ,  H01R12/62 ,  H05K1/00 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/32

    CPC classification number: H01R4/04 ,  H01R12/62 ,  H05K1/189 ,  H05K3/326 ,  H05K1/0286 ,  H05K1/0289 ,  H05K1/118 ,  H05K1/145 ,  H05K1/182 ,  H05K2201/052 ,  H05K2201/09072 ,  H05K2201/09081 ,  H05K2201/091 ,  H05K2201/09172 ,  H05K2201/10393 ,  H05K2201/1059 ,  H05K2201/10689 ,  Y10S439/912

    Abstract: A method of manufacturing an electrical circuit system comprising electrical conductors on a flexible film and an article of manufacture made thereby, which may be used in place of printed circuit boards and which conductors form connector means for readily connecting to the leads of one or more sides of an electronic package. The electrical conductors also form a means for selectably connecting each electrical conductor from each pin to a selected input or output conductor, comprising a first and second plurality of conductors, such as a matrix having a column of conductors and a row of conductors. The electrical circuit system may be manufactured by numerous methods such as applying a conductive ink or paint by screening, photolithography or drawn by a digital plotter on a plastic film, such as Mylar. The film may include electrical edge connection means to provide input or output to or from said conductors. All or most of the system is integral, thus forming the conductors and the in-line connector portion of the conductors in continuum, using the same conductive material, such as ink, or paint and the same dielectric material, such as ink, or paint. A dielectric covers the appropriate portion of the system.

    Abstract translation: 一种制造电路系统的方法，该电路系统包括柔性膜上的电导体和由此制成的制品，其可用于代替印刷电路板，并且哪些导体形成用于容易地连接到一个或多个侧面的引线的连接器装置 的电子包装。 电导体还形成用于将每个引脚的每个电导体可选地连接到选定的输入或输出导体的装置，该导体包括第一和第二多个导体，例如具有导体列和一排导体的矩阵。 电路系统可以通过许多方法来制造，例如通过筛选，光刻或通过数字绘图仪在诸如Mylar的塑料膜上涂抹导电油墨或涂料。 该胶片可以包括电边缘连接装置，以向所述导体提供输入或输出。 所有或大部分系统是一体的，因此使用相同的导电材料（例如墨水或涂料）和相同的电介质材料（例如油墨或油漆）在连续体中形成导体的导体和直列连接器部分 。 电介质覆盖系统的适当部分。

    PROTECTIVE COVER FOR PRINTED CIRCUIT BOARD
    40.
    发明申请
    PROTECTIVE COVER FOR PRINTED CIRCUIT BOARD 有权
    印刷电路板保护罩

    公开(公告)号：US20160374225A1

    公开(公告)日：2016-12-22

    申请号：US15157540

    申请日：2016-05-18

    Applicant: ZF Friedrichshafen AG

    Inventor： Dirk RASCHKE

    IPC: H05K7/14 ,  H05K1/09 ,  H05K5/03

    CPC classification number: H05K1/0257 ,  H05K2201/09172 ,  H05K2201/10287 ,  H05K2201/10446

    Abstract: A voltage protection for printed circuit boards is provided, which is slotted on one end, such that it has printed circuit board strips, a mount, which is configured to at least partially receive the printed circuit board, and a voltage protection cover, which is configured to be connected to the mount and the printed circuit board, such that a chamber system is formed, in which each printed circuit board strip is disposed inside a chamber, which is formed by the connection between the mount and the voltage protection cover.

    Abstract translation: 提供印刷电路板的电压保护，其在一端开槽，使得其具有印刷电路板条，安装件，其构造成至少部分地接收印刷电路板，以及电压保护盖，其是 被配置为连接到安装件和印刷电路板，使得形成室系统，其中每个印刷电路板条被设置在通过安装件和电压保护盖之间的连接形成的室内。

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