公开(公告)号：US20110139489A1

公开(公告)日：2011-06-16

申请号：US12772469

申请日：2010-05-03

Applicant: Hee-Soo Yoon ,  Dong-Hwan Lee ,  Kyoung-Ho Lee ,  Yoon-Dong Kim ,  Su-Bong Jang

Inventor： Hee-Soo Yoon ,  Dong-Hwan Lee ,  Kyoung-Ho Lee ,  Yoon-Dong Kim ,  Su-Bong Jang

IPC: H05K1/00

CPC classification number: H05K1/0227 ,  H05K1/0262 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09663

Abstract: A printed circuit board is disclosed. The printed circuit board in accordance with an embodiment of the present invention can include an insulation substrate, a first ground, which is formed on one surface of the insulation substrate and connected to a first power source, a second ground, which is formed on one surface of the insulation substrate and connected to a second power source, a separator, which separates the first ground from the second ground, a first signal line, which is stacked on at least one of the first ground and the second ground, and a second signal line, which is stacked on at least one of the first ground and the second ground and is adjacent to the first signal line. The separator can include a curved part, which is bent in between the first signal line and the second signal line.

Abstract translation: 公开了印刷电路板。 根据本发明的实施例的印刷电路板可以包括绝缘基板，第一接地，其形成在绝缘基板的一个表面上并连接到第一电源，第二接地形成在第一接地 绝缘基板的表面并且连接到第二电源，将第一接地与第二接地分离的隔离件，堆叠在第一接地和第二接地中的至少一个上的第一信号线，以及第二接地 信号线，其堆叠在第一接地和第二接地中的至少一个上并且与第一信号线相邻。 分离器可以包括在第一信号线和第二信号线之间弯曲的弯曲部分。

公开(公告)号：US07901248B2

公开(公告)日：2011-03-08

申请号：US12386641

申请日：2009-04-21

Applicant: Juergen Lappoehn

Inventor： Juergen Lappoehn

IPC: H01R13/648

CPC classification number: H05K1/0219 ,  H01R12/716 ,  H01R12/724 ,  H01R13/6585 ,  H05K1/0237 ,  H05K3/308 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10189 ,  H05K2201/1059

Abstract: A multipolar plug connector for establishing contact with a multilayer board includes signal contacts that are assigned a first and at least one second screen contact element and are arranged adjacent to the signal contact. Recesses are provided at least on the uppermost Layer of the multilayer board which are suitably sized so as to receive and to lead through at least two screen contact elements assigned to neighboring signal contacts.

Abstract translation: 用于与多层板建立接触的多极插头连接器包括被分配有第一和至少一个第二屏幕接触元件并被布置成与信号触点相邻的信号触点。 至少在多层板的最上层设置有适当尺寸以便接收和引导分配给相邻信号触点的至少两个屏幕接触元件的凹陷。

公开(公告)号：US07873933B2

公开(公告)日：2011-01-18

申请号：US11936673

申请日：2007-11-07

Applicant: Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

Inventor： Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

IPC: G06F17/50 ,  H03K17/693

CPC classification number: H05K1/0265 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10189 ,  Y10T29/49156

Abstract: A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract translation: 用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。 在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。 连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。 槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。 所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

公开(公告)号：US07847318B2

公开(公告)日：2010-12-07

申请号：US12406009

申请日：2009-03-17

Applicant: Naohiro Hirose ,  Honjin En

Inventor： Naohiro Hirose ,  Honjin En

IPC: H01L29/40 ,  H05K7/20

CPC classification number: H01L29/40 ,  H01L21/4763 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/03 ,  H05K3/064 ,  H05K3/244 ,  H05K3/382 ,  H05K3/403 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09645 ,  H05K2201/09681 ,  H05K2203/1178

Abstract: Mesh holes 35a and 59a of upper solid layers 35 and upper solid layers 59 are formed to overlie on one another, so that the insulating properties of interlayer resin insulating layers 50 are not lowered. Here, the diameter of each mesh hole is preferably 75 to 300 μm. The reason is as follows. If the diameter of the mesh hole is less than 75 μm, it is difficult to overlay the upper and lower mesh holes on one another. If the diameter exceeds 300 μm, the insulating properties of the interlayer resin insulating layers deteriorate. In addition, the distance between the mesh holes is preferably 100 to 2000 μm. The reason is as follows. If the distance is less than 100 μm, the solid layer cannot function. If the distance exceeds 2000 μm, the deterioration of the insulating properties of the interlayer resin insulating film occurs.

Abstract translation: 上固体层35和上固体层59的网孔35a和59a形成为彼此重叠，使得层间树脂绝缘层50的绝缘性能不降低。 这里，每个网孔的直径优选为75〜300μm。 原因如下。 如果网孔的直径小于75μm，则难以将上，下网孔叠置在一起。 如果直径超过300μm，则层间树脂绝缘层的绝缘性变差。 此外，网孔之间的距离优选为100〜2000μm。 原因如下。 如果距离小于100μm，则固体层不能起作用。 如果距离超过2000μm，则发生层间树脂绝缘膜的绝缘性的劣化。

公开(公告)号：US07797663B2

公开(公告)日：2010-09-14

申请号：US11696659

申请日：2007-04-04

Applicant: Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

Inventor： Steven C. Bird ,  Varoujan Malian ,  Mudasir Ahmad ,  Charles H. Casale ,  Danlu Tang

IPC: G06F17/50

CPC classification number: G01R31/2818 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/0262 ,  H05K1/0268 ,  H05K1/113 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3457 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K2201/0367 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/09663 ,  H05K2201/10333 ,  H05K2201/10462 ,  H05K2201/10484 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: Methods and apparatus for accessing a high speed signal routed on a conductive trace on an internal layer of a printed circuit board (PCB) using high density interconnect (HDI technology) are provided. The conductive trace may be coupled to a microvia (μVia) having a conductive dome disposed above the outer layer pad of the μVia. In-circuit test (ICT) fixtures or high speed test probes may interface with the conductive dome to test the high speed signal with decreased reflection loss and other parasitic effects when compared to conventional test points utilizing plated through-hole (PTH) technology.

Abstract translation: 提供了使用高密度互连（HDI技术）访问在印刷电路板（PCB）的内层上的导电迹线上路由的高速信号的方法和装置。 导电迹线可以耦合到具有设置在μVia的外层焊盘上方的导电圆顶的微孔（μVia）。 与使用电镀通孔（PTH）技术的常规测试点相比，在线测试（ICT）固定装置或高速测试探头可与导电圆顶接口以测试具有降低的反射损耗和其他寄生效应的高速信号。

公开(公告)号：US07765673B2

公开(公告)日：2010-08-03

申请号：US12124388

申请日：2008-05-21

Applicant: Jean-Francois Fauh ,  Claude Gomez ,  Andre Lecerf ,  Denis G. Roman

Inventor： Jean-Francois Fauh ,  Claude Gomez ,  Andre Lecerf ,  Denis G. Roman

IPC: G01R31/28

CPC classification number: H05K1/0265 ,  H05K1/0268 ,  H05K1/115 ,  H05K2201/093 ,  H05K2201/0979 ,  Y10T29/49004 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method and system for improving power distribution and/or current measurement on a printed circuit board is disclosed. According to the invention, a first power plane adapted for current measurement includes a first segment to which a current source is connected and a second segment to which other devices may be connected, forming the current load. A third segment is used to measure the current between the first segment and the second segment through two vias that link two points of the third segment to, preferably, two pads of the external layer. In a preferred embodiment, vias are connected to the first segment so that current flow in the third segment is linear, to improve and simplify current determination. The resistivity between the pair of vias may be computed or estimated using calibrated currents.

Abstract translation: 公开了一种用于改善印刷电路板上的配电和/或电流测量的方法和系统。 根据本发明，适用于电流测量的第一电源平面包括电流源连接到的第一段和可连接其它设备的第二段，形成电流负载。 第三段用于通过将第三段的两个点连接到外层的两个焊盘的两个通孔来测量第一段和第二段之间的电流。 在优选实施例中，通孔连接到第一段，使得第三段中的电流是线性的，以改善和简化电流确定。 一对通孔之间的电阻率可以使用校准电流来计算或估计。

公开(公告)号：US20100180437A1

公开(公告)日：2010-07-22

申请号：US12603071

申请日：2009-10-21

Applicant: William E. McKinzie, III

Inventor： William E. McKinzie, III

IPC: H01R43/00

CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09609 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband. Coplanar EBG structures may be integrated into power distribution networks of printed wiring boards for broadband suppression of electromagnetic noise.

Abstract translation: 用于宽带抑制印刷电路板上的噪声的混合电磁带隙（EBG）结构包括通过串联电感互连到电网中的共面贴片阵列，以及将共面贴片连接到第二导电平面的相应阵列的分流LC网络。 串联电感和并联谐振通孔的组合降低了基波阻带的截止频率。 串联电感和分流电容可以使用表面贴装元件技术或印刷迹线实现。 补片也可以通过共面耦合传输线相互连接。 可以通过在与传输线相对布置的第二导电平面中形成槽，降低截止频率并增加基带阻带的带宽来增加耦合线的偶模和奇模阻抗。 共面EBG结构可以集成到用于宽带抑制电磁噪声的印刷线路板的配电网络中。

公开(公告)号：US20100175911A1

公开(公告)日：2010-07-15

申请号：US12354243

申请日：2009-01-15

Applicant: Ralph Morrison

Inventor： Ralph Morrison

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H05K1/0289 ,  H05K1/0219 ,  H05K1/0224 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09336 ,  H05K2201/09681 ,  Y10T29/49124

Abstract: Devices and methods are described for high-speed two layer and multilayer circuit boards. A device comprises a single circuit board or a circuit board made by laminating several two layer circuit boards. The device comprises mounting pads attached to the circuit board. The device comprises trace arrays that electrically couple the mounting pads. The trace arrays include a first trace array attached to a first side of each circuit board layer and a second trace array attached to a second side of each circuit board layer. Each trace array comprises conductive traces, and the conductive traces are arranged so each signal trace is positioned between combinations of ground traces and power traces to control the characteristic impedance of each logic or signal path. The arrays on the layers of the board are interconnected by vias to form a pseudo ground and power plane.

Abstract translation: 描述了高速双层和多层电路板的设备和方法。 一种器件包括单个电路板或通过层压几个两层电路板制成的电路板。 该装置包括安装在电路板上的安装垫。 该器件包括电连接安装焊盘的迹线阵列。 迹线阵列包括附接到每个电路板层的第一侧的第一迹线阵列和附接到每个电路板层的第二侧的第二迹线阵列。 每个迹线阵列包括导电迹线，并且布置导电迹线，使得每个信号迹线位于接地迹线和功率迹线的组合之间，以控制每个逻辑或信号路径的特征阻抗。 板上的阵列通过通孔相互连接，形成伪地面和电源平面。

公开(公告)号：US20100132984A1

公开(公告)日：2010-06-03

申请号：US12629162

申请日：2009-12-02

Applicant: Yuya Narazako ,  Kazunari Sakaki

Inventor： Yuya Narazako ,  Kazunari Sakaki

IPC: H05K1/03 ,  H05K1/16

CPC classification number: H05K1/0216 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/09972

Abstract: In order to reduce noise propagating from a digital signal circuit to an analog signal circuit, a multilayer printed circuit board includes a first digital signal circuit formed in a first region of a front surface, a first analog signal circuit formed in a second region of the front surface, a second digital signal circuit formed at a back surface corresponding to the first region, a second analog signal circuit formed at the back surface corresponding to the second region; an analog ground circuit formed between the front surface and the back surface to ground the first analog signal circuit and the second analog signal circuit, and a first digital ground circuit arranged between the first digital signal circuit and the analog ground circuit and a second digital ground circuit arranged between the second digital signal circuit and the analog ground circuit to ground the first digital signal circuit and the second digital signal circuit.

Abstract translation: 为了减少从数字信号电路传播到模拟信号电路的噪声，多层印刷电路板包括形成在前表面的第一区域中的第一数字信号电路，形成在第一区域的第一模拟信号电路 形成在与第一区域对应的背面的第二数字信号电路，形成在与第二区域对应的背面的第二模拟信号电路; 形成在所述前表面和所述后表面之间以将所述第一模拟信号电路和所述第二模拟信号电路接地的模拟接地电路，以及布置在所述第一数字信号电路和所述模拟地电路之间的第一数字接地电路和第二数字接地 布置在第二数字信号电路和模拟地电路之间以将第一数字信号电路和第二数字信号电路接地的电路。

公开(公告)号：US07721238B2

公开(公告)日：2010-05-18

申请号：US11231642

申请日：2005-09-21

Applicant: Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

Inventor： Norman L. Rogers ,  John W. Hoffman ,  Jun Feng ,  Charles Krauter

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  H05K1/0206 ,  H05K1/029 ,  H05K1/0295 ,  H05K1/111 ,  H05K1/114 ,  H05K3/0005 ,  H05K3/0064 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09418 ,  H05K2201/09454 ,  H05K2201/09663 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10636 ,  H05K2203/173 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124

Abstract: A method and apparatus for inputting a plurality of different circuit schematics designed with printed circuit board (PCB) mountable components; extracting circuit topologies for said plurality of different circuit schematics; transforming said extracted circuit topologies to a fixed number of connection points; and generating a configurable circuit PCB physical layout pattern having said fixed number of connection points such that said PCB mountable components when positioned on one or more of said fixed number of connection points can implement any circuit represented by said plurality of different circuit schematics.

Abstract translation: 一种用于输入设计有印刷电路板（PCB）可安装部件的多个不同电路原理图的方法和装置; 提取用于所述多个不同电路原理图的电路拓扑; 将所述提取的电路拓扑转换为固定数量的连接点; 以及生成具有所述固定数量的连接点的可配置电路PCB物理布局图案，使得当位于所述固定数量的连接点中的一个或多个连接点上时所述PCB可安装部件可以实现由所述多个不同电路原理图表示的任何电路。