公开(公告)号：US20160204531A1

公开(公告)日：2016-07-14

申请号：US14916473

申请日：2014-09-04

Applicant: FUJIKURA LTD. ,  DDK LTD.

Inventor： Yuki ISHIDA ,  Masayuki SUZUKI ,  Yuki NAKANO ,  Harunori URAI ,  Norifumi NAGAE

IPC: H01R12/73 ,  H05K1/11

CPC classification number: H01R12/73 ,  H01R12/77 ,  H01R12/88 ,  H05K1/111 ,  H05K1/117 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09409 ,  H05K2201/10189

Abstract: A printed wiring board (1) includes: a base substrate (3); a plurality of pads (15a, 17a) for electrical connection that are disposed at one surface side of the base substrate (3) and at a connection end portion (13) to be connected with another electronic component (50); wirings (9, 11) that are connected with the pads (15a, 17a); and engageable parts (28, 29) that are formed at side edge parts of the connection end portion (13) and are to be engaged with engagement parts (58) of the other electronic component (50) in the direction of disconnection. The flexible printed wiring board (1) further includes: reinforcement layers (31, 32) that are disposed at the one surface side of the base substrate (3) and at a frontward side with respect to the engageable parts (28, 29) when viewed in the direction of connection with the other electronic component and that are formed integrally with the pads (15a); and insulating layers (34, 35) that cover the reinforcement layers (31, 32).

Abstract translation: 印刷电路板（1）包括：基底（3）; 多个用于电连接的焊盘（15a，17a），其设置在所述基底基板（3）的一个表面侧和连接端部（13）处以与另一个电子部件（50）连接; 与焊盘（15a，17a）连接的布线（9,11）; 以及形成在连接端部（13）的侧边缘部分处并且沿着断开方向与另一个电子部件（50）的接合部分（58）接合的可接合部分（28,29）。 柔性印刷电路板（1）还包括：加强层（31,32），其设置在基底基板（3）的一个表面侧，并且相对于可接合部件（28,29）在前侧， 从与其他电子部件的连接方向观察并与焊盘（15a）一体形成; 和覆盖加强层（31,32）的绝缘层（34,35）。

公开(公告)号：US09390764B2

公开(公告)日：2016-07-12

申请号：US14016211

申请日：2013-09-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Hung-I Chung ,  Chang-Chih Chen

IPC: G11C5/04 ,  H05K1/11 ,  H01R12/71 ,  H01R13/66

CPC classification number: G11C5/04 ,  H01R12/714 ,  H01R13/6683 ,  H05K1/117 ,  H05K2201/094 ,  H05K2201/09409 ,  Y10T29/49069

Abstract: A storage apparatus including a storage element and a fitting member is provided. The storage element includes a body, a first pad set and a second pad set. The first and the second pad sets are exposed out of the body and located at opposite sides of the body. The fitting member comprises a first terminal set and a second terminal set electrically connected to each other. The storage element is detachably assembled to the fitting member. The first terminal set electrically connected to the first pad set and the second terminal set located between the first pad set and the second pad set, the second terminal set and the second pad set form a connecting interface of the storage apparatus that the storage apparatus is used for being electrically connected to an external apparatus. A production method of the storage apparatus is further provided.

Abstract translation: 提供了包括存储元件和配件的存储设备。 存储元件包括主体，第一焊盘组和第二焊盘组。 第一和第二垫组从身体露出并位于身体的相对侧。 配合构件包括彼此电连接的第一端子组和第二端子组。 存储元件可拆卸地组装到配件上。 电连接到第一焊盘组的第一端子组和位于第一焊盘组和第二焊盘组之间的第二端子组，第二端子组和第二焊盘组形成存储装置的连接接口， 用于电连接到外部设备。 还提供了一种存储装置的制造方法。

公开(公告)号：US20160066426A1

公开(公告)日：2016-03-03

申请号：US14471905

申请日：2014-08-28

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsien-Wei Chen

IPC: H05K1/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/48 ,  H01L21/56 ,  H05K3/40 ,  H01L21/48 ,  H01L21/52 ,  H01L25/00 ,  H01L25/065 ,  H05K1/11 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05572 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1144 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1712 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/181 ,  H05K1/0284 ,  H05K1/0313 ,  H05K1/111 ,  H05K1/181 ,  H05K3/40 ,  H05K2201/09409 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

Abstract translation: 公开了半导体器件的封装方法及其封装方法。 在一些实施例中，装置包括设置在包装装置上的包装装置和接触垫。 接触垫排列成行和列的阵列。 接触垫包括靠近包装设备的周边区域的第一接触垫和设置在包装设备的内部区域中的第二接触垫。 围绕第二接触垫设置连续的坝结构。 接触垫包括用于半导体器件的安装区域。

公开(公告)号：US09220167B2

公开(公告)日：2015-12-22

申请号：US14623689

申请日：2015-02-17

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi Shimizu ,  Masato Tanaka ,  Toshinori Koyama ,  Akio Rokugawa

IPC: H01L23/12 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46 ,  H01L23/15 ,  H01L23/538

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/12044 ,  H05K1/0271 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/045 ,  H05K2201/09409 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/09827 ,  H05K2201/10204 ,  H05K2201/10674 ,  Y10T29/49162 ,  H01L2924/00

Abstract: A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V1/V2 is from 0.8 to 1.5, where V1 represents the volume of the wiring layers forming the entire second wiring structure, and V2 represents the volume of the bottom wiring layer in the first wiring structure.

Abstract translation: 布线基板包括第一布线结构，堆叠在第一布线结构的上表面上的第二布线结构和堆叠在第一布线结构的下表面上的最外绝缘层。 最外层绝缘层覆盖形成第一布线结构的布线层的底部布线层的一部分。 第二布线结构具有比第一布线结构高的布线密度。 体积比V1 / V2为0.8〜1.5，其中V1表示形成整个第二布线结构的布线层的体积，V2表示第一布线结构中底布线层的体积。

公开(公告)号：US09173289B2

公开(公告)日：2015-10-27

申请号：US14628455

申请日：2015-02-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Noboru Kato ,  Jun Sasaki ,  Satoshi Ishino

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09

CPC classification number: H05K1/0281 ,  H05K1/024 ,  H05K1/028 ,  H05K1/0298 ,  H05K1/032 ,  H05K1/09 ,  H05K2201/0141 ,  H05K2201/057 ,  H05K2201/0715 ,  H05K2201/09018 ,  H05K2201/09409

Abstract: A multilayer substrate that retains a curved state without causing fluctuations in electrical characteristics includes a main body including a plurality of insulating sheets to be stacked and made of a flexible material. A signal wire extends in the main body. A ground conductor is provided at a positive-direction side in a z-axis direction relative to the signal wire in the main body, and overlaps the signal line in a plan view seen from the z-axis direction. A ground conductor is provided on a negative-direction side in the z-axis direction relative to the signal wire in the main body, and overlaps the signal line in a plan view seen from the z-axis direction. The state in which the main body is curved so that the signal wire defines an arc is retained by plastic deformation of the ground conductors.

公开(公告)号：US20150253820A1

公开(公告)日：2015-09-10

申请号：US14721942

申请日：2015-05-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyojae BANG ,  Dogeun KIM ,  Hongkyun KIM ,  Youngbok JEON

IPC: G06F1/18

CPC classification number: H05K5/0026 ,  G06F1/18 ,  G06F1/185 ,  G06K7/0047 ,  H01R12/57 ,  H01R12/721 ,  H01R13/00 ,  H01R23/70 ,  H01R27/00 ,  H05K1/0295 ,  H05K1/11 ,  H05K1/117 ,  H05K1/181 ,  H05K3/10 ,  H05K3/303 ,  H05K3/3405 ,  H05K7/02 ,  H05K13/00 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/09954 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10446 ,  Y10S439/946 ,  Y10S439/951 ,  Y10T29/49124 ,  Y10T29/49147

Abstract: Example embodiments are directed to circuit boards, connectors, cases, circuit board assemblies, case assemblies, devices and methods of manufacturing the same, which are common to at least two different form factors.

公开(公告)号：US20150245473A1

公开(公告)日：2015-08-27

申请号：US14623689

申请日：2015-02-17

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi SHIMIZU ,  Masato TANAKA ,  Toshinori KOYAMA ,  Akio ROKUGAWA

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/03 ,  H05K1/11 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K1/0298 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5385 ,  H01L23/5389 ,  H01L2224/16225 ,  H01L2924/12044 ,  H05K1/0271 ,  H05K1/036 ,  H05K1/0366 ,  H05K1/113 ,  H05K1/115 ,  H05K1/141 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4602 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/045 ,  H05K2201/09409 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/09827 ,  H05K2201/10204 ,  H05K2201/10674 ,  Y10T29/49162 ,  H01L2924/00

Abstract: A wiring substrate includes a first wiring structure, a second wiring structure stacked on an upper surface of the first wiring structure, and an outermost insulating layer stacked on a lower surface of the first wiring structure. The outermost insulating layer covers a part of a bottom wiring layer of the wiring layers forming the first wiring structure. The second wiring structure has a wiring density higher than that of the first wiring structure. A volume ratio V1/V2 is from 0.8 to 1.5, where V1 represents the volume of the wiring layers forming the entire second wiring structure, and V2 represents the volume of the bottom wiring layer in the first wiring structure.

Abstract translation: 布线基板包括第一布线结构，堆叠在第一布线结构的上表面上的第二布线结构和堆叠在第一布线结构的下表面上的最外绝缘层。 最外层绝缘层覆盖形成第一布线结构的布线层的底部布线层的一部分。 第二布线结构具有比第一布线结构高的布线密度。 体积比V1 / V2为0.8〜1.5，其中V1表示形成整个第二布线结构的布线层的体积，V2表示第一布线结构中底布线层的体积。

公开(公告)号：US09084372B2

公开(公告)日：2015-07-14

申请号：US13749070

申请日：2013-01-24

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Shigetsugu Muramatsu ,  Hiroshi Shimizu ,  Yasuyoshi Horikawa

IPC: H05K7/00 ,  F21V7/00 ,  C25D5/02 ,  H05K7/20 ,  H05K3/46 ,  F21K99/00 ,  H05K1/02 ,  H05K1/05 ,  H05K3/34

CPC classification number: H05K7/2039 ,  F21K9/90 ,  F21V7/00 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K1/056 ,  H05K3/3452 ,  H05K3/46 ,  H05K2201/0191 ,  H05K2201/09409 ,  H05K2201/099 ,  H05K2201/10106 ,  H05K2201/2054

Abstract: There is provided a wiring substrate. The wiring substrate includes: a heat sink; an insulating layer on the heat sink; first and second wiring patterns on the insulating layer to be separated from each other at a certain interval; a first reflective layer including a first opening on the insulating layer so as to cover the first and second wiring patterns, wherein a portion of the first and second wiring patterns is exposed from the first opening, and wherein the portion of the first and second wiring patterns is defined as a mounting region on which a light emitting element is to be mounted; and a second reflective layer on the insulating layer, wherein the second reflective layer is interposed between the first and second wiring patterns. A thickness of the second reflective layer is smaller than that of the first reflective layer.

Abstract translation: 提供了布线基板。 布线基板包括：散热器; 散热器上的绝缘层; 绝缘层上的第一和第二布线图案以一定间隔彼此分离; 第一反射层，包括在绝缘层上的第一开口，以覆盖第一和第二布线图案，其中第一和第二布线图案的一部分从第一开口露出，并且其中第一和第二布线的部分 图案被定义为要安装发光元件的安装区域; 以及在绝缘层上的第二反射层，其中第二反射层介于第一和第二布线图案之间。 第二反射层的厚度小于第一反射层的厚度。

公开(公告)号：US08952518B2

公开(公告)日：2015-02-10

申请号：US14006527

申请日：2012-07-20

Applicant: Mahiro Tsujino ,  Manabu Miyahara

Inventor： Mahiro Tsujino ,  Manabu Miyahara

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/057 ,  H01L23/10

CPC classification number: H01L24/42 ,  H01L23/057 ,  H01L23/10 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/16195 ,  H01L2924/16251 ,  H01L2924/171 ,  H05K3/3442 ,  H05K2201/09172 ,  H05K2201/09181 ,  H05K2201/09409 ,  H05K2201/09909 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device housing package includes a base body having, on its upper surface, a mounting region of a semiconductor device; a frame body having a frame-like portion disposed on the upper surface of the base body, surrounding the mounting region, and an opening penetrating through from an inner side of the frame-like portion to an outer side thereof; a flat plate-like insulating member disposed in the opening, extending from an interior of the frame body to an exterior thereof; wiring conductors disposed on an upper surface of the insulating member, extending from the interior of the frame body to the exterior thereof; and a metallic film disposed on a part of the upper surface of the insulating member, the metallic film lying outside the frame body surrounding the wiring conductors.

Abstract translation: 半导体器件壳体封装包括：基体，其上表面具有半导体器件的安装区域; 框架体，其具有设置在基体的上表面上的框状部分，围绕安装区域，以及从框状部分的内侧穿过其外侧的开口; 设置在所述开口中的平板状绝缘构件，从所述框体的内部延伸到其外部; 布线导体设置在绝缘构件的上表面上，从框体的内部延伸到其外部; 以及设置在所述绝缘构件的上表面的一部分上的金属膜，所述金属膜位于围绕所述布线导体的框架体的外侧。

公开(公告)号：US20150027977A1

公开(公告)日：2015-01-29

申请号：US14341004

申请日：2014-07-25

Applicant: KYOCERA SLC Technologies Corporation

Inventor： Kohichi OHSUMI ,  Sumiko NOGUCHI

IPC: H05K3/06 ,  H05K3/07

CPC classification number: H05K3/243 ,  H05K3/108 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/09409 ,  H05K2203/0574 ,  H05K2203/0597

Abstract: A manufacturing method includes a step of forming a first plating mask on a base metal layer, a step of forming a main conductor layer on the base metal layer exposed from the first plating mask, a step of forming a second plating mask on them, a step of attaching a metal plating layer to an upper surface of the main conductor layer exposed from the second plating mask, a step of removing the first and second plating masks, a step of etching away a portion of the base metal layer to which the main conductor layer is not attached, and a step of forming a solder resist layer.

Abstract translation: 一种制造方法包括在基底金属层上形成第一电镀掩模的步骤，在从第一电镀掩模露出的基底金属层上形成主导体层的步骤，在其上形成第二电镀掩模的步骤， 将金属镀层附着到从第二电镀掩模露出的主导体层的上表面的步骤，去除第一和第二电镀掩模的步骤，蚀刻掉主金属层的一部分的步骤 未附着导体层，以及形成阻焊层的工序。