公开(公告)号：US09730327B1

公开(公告)日：2017-08-08

申请号：US14657032

申请日：2015-03-13

Applicant: Amkor Technology, Inc.

Inventor： Akito Yoshida ,  Mahmoud Dreiza ,  Curtis Michael Zwenger

IPC: H05K1/18 ,  H05K3/36 ,  H01L23/00 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H05K1/11 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/1191 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/16055 ,  H01L2224/1607 ,  H01L2224/16113 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2924/01029 ,  H01L2924/01079 ,  H05K1/14 ,  H05K1/181 ,  H05K1/184 ,  H05K1/185 ,  H05K3/303 ,  H05K3/34 ,  H05K3/3436 ,  H05K3/363 ,  H05K3/4007 ,  H05K2201/10515 ,  H05K2201/10977 ,  H05K2203/043 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A

公开(公告)号：US09717157B2

公开(公告)日：2017-07-25

申请号：US14617523

申请日：2015-02-09

Applicant: Micron Technology, Inc.

Inventor： Kevin Gibbons ,  Tracy V. Reynolds ,  David J. Corisis

IPC: H05K1/18 ,  H05K7/02 ,  H05K3/34 ,  H01L25/065 ,  H01L25/10 ,  H01L23/00 ,  H05K1/11 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L24/83 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19104 ,  H05K1/111 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3436 ,  H05K7/02 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10727 ,  H05K2203/1572 ,  Y10T29/49126 ,  Y10T29/4913 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Computer modules with small thicknesses and associated methods of manufacturing are disclosed. In one embodiment, the computer modules can include a module substrate having a module material and an aperture extending at least partially into the module material. The computer modules can also include a microelectronic package carried by the module substrate. The microelectronic package includes a semiconductor die carried by a package substrate. At least a portion of the semiconductor die extends into the substrate material via the aperture.

公开(公告)号：US09716060B2

公开(公告)日：2017-07-25

申请号：US14692769

申请日：2015-04-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K3/00 ,  H05K3/32 ,  H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K1/02 ,  H05K3/10 ,  H05K3/46 ,  H01L23/31 ,  H01L21/683

CPC classification number: H01L23/49838 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32058 ,  H01L2224/32105 ,  H01L2224/32106 ,  H01L2224/32237 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2924/15313 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104 ,  H05K1/0231 ,  H05K1/185 ,  H05K1/186 ,  H05K1/189 ,  H05K3/0026 ,  H05K3/007 ,  H05K3/108 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/0665

Abstract: The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method includes: forming a first wiring layer on a carrier; removing the carrier and forming the first wiring layer on a bonding carrier; disposing an electronic component on the first wiring layer; forming an encapsulating layer, a second wiring layer and an insulating layer on the first wiring layer; disposing a chip on the electronic component and the second wiring layer; and forming a covering layer that covers the chip. The present invention can effectively reduce the thickness of the package structure and the electronic component without using adhesives.

公开(公告)号：US09665122B2

公开(公告)日：2017-05-30

申请号：US14845573

申请日：2015-09-04

Applicant: Heung Kyu Kwon ,  Hae Gu Lee ,  Byeong Yeon Cho

Inventor： Heung Kyu Kwon ,  Hae Gu Lee ,  Byeong Yeon Cho

IPC: H01L23/48 ,  G06F1/16 ,  H01L23/498 ,  H01L23/544 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H05K1/02 ,  H05K3/34

CPC classification number: G06F1/1601 ,  G06F1/16 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/16 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2223/54406 ,  H01L2223/54426 ,  H01L2223/54433 ,  H01L2223/54486 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/18161 ,  H05K1/0269 ,  H05K3/3436 ,  H05K2201/10159 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2201/10977 ,  H01L2224/81

Abstract: A semiconductor package includes a printed circuit board (PCB), a chip bonded to the PCB, a mold protecting the chip and exposing a backside surface of the chip, via openings extending in the mold to expose first contacts bonded to the PCB, and at least one first marking inscribed in a marking region of the mold between the backside surface of the chip and the vias. The mold has an exposed molded underfill (eMUF) structure covering the sides of the chip while exposing the backside surface of the chip. A PoP package includes a top package stacked on and electrically connected to the semiconductor package.

公开(公告)号：US09648746B2

公开(公告)日：2017-05-09

申请号：US14663445

申请日：2015-03-19

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Heung Kil Park ,  Sang Soo Park

IPC: H05K7/00 ,  H05K1/18 ,  H05K3/34 ,  H05K1/02

CPC classification number: H05K1/181 ,  H05K1/0233 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/1003 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611 ,  Y02P70/613

Abstract: There is provided a composite electronic component and a board having the same, and the composite electronic component may include: an interposer board, and first and second electronic components mounted on upper and lower surfaces of the interposer board, respectively, and first and second electronic components are electrically connected to each other by an electrical connection part provided on the interposer board.

公开(公告)号：US09629249B2

公开(公告)日：2017-04-18

申请号：US14939102

申请日：2015-11-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeru Tago ,  Yuki Wakabayashi ,  Hirofumi Shinagawa

IPC: H05K1/18 ,  H01L23/538 ,  H01L23/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K3/46

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/11 ,  H05K1/186 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/10515

Abstract: A component-embedded substrate includes a first embedded component positioned in a layer close to a mounting electrode and a second embedded component positioned in a layer farther away from the mounting electrode than the first embedded component. The first and second embedded components include electrically connected terminals. Each resin film of the substrate is formed of thermoplastic resin. The first embedded component has more terminals than the second embedded component. Many of the internal wires from the first and second embedded component extend towards a mounting surface where the mounting electrode is provided. However, since in plan view the area of the first embedded component is smaller than the second embedded component, and the first embedded component is disposed closer to the mounting surface than the second embedded component, there is space for routing the internal wires at the side of the mounting surface of the substrate.

公开(公告)号：US20170105303A1

公开(公告)日：2017-04-13

申请号：US15296813

申请日：2016-10-18

Applicant: Amphenol Corporation

Inventor： Donald A. GIRARD, JR. ,  Robert Auger ,  Mark W. Gailus

IPC: H05K5/02 ,  H05K5/00 ,  H05K1/18 ,  H05K5/06

CPC classification number: H05K5/0247 ,  H01R13/6466 ,  H01R13/6473 ,  H01R13/6625 ,  H05K1/0231 ,  H05K1/181 ,  H05K3/301 ,  H05K5/0021 ,  H05K5/0217 ,  H05K5/065 ,  H05K13/00 ,  H05K2201/10015 ,  H05K2201/10515

Abstract: An adapter has two conductors each with a U-shaped bend forming upper longer legs and lower shorter legs. The conductors face each other with the longer legs linearly aligned with each other and the shorter legs aligned with each other, thereby forming a first gap between the longer legs and a second gap between the shorter legs. The first gap is substantially smaller than the second gap, so that an electrical package can be placed across the first gap to contact the two upper longer legs, while the two shorter legs are spaced further apart to span a larger gap between conductors of a connector. Thus, the adapter enables the electrical package to be connected to conductors having a gap that is larger than the electrical package.

公开(公告)号：US09615456B2

公开(公告)日：2017-04-04

申请号：US14809570

申请日：2015-07-27

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Terrence Caskey ,  Reynaldo Co ,  Ellis Chau

IPC: H05K1/09 ,  H05K1/11 ,  H01L23/528 ,  H05K1/02 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H05K1/18 ,  H01L25/03 ,  H01L21/56 ,  H01L23/00

CPC classification number: H05K1/11 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/528 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/32225 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/10515 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

公开(公告)号：US20170047261A1

公开(公告)日：2017-02-16

申请号：US15335260

申请日：2016-10-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun-Lin Lu ,  Kai-Chiang Wu ,  Yen-Ping Wang ,  Shih-Wei Liang ,  Ching-Feng Yang

IPC: H01L23/24 ,  H01L25/10 ,  H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/24 ,  H01L21/481 ,  H01L21/4885 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H05K1/181 ,  H05K2201/049 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2201/2036 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An interposer may comprise a metal layer above a substrate. A dam or a plurality of dams may be formed above the metal layer. A dam surrounds an area of a size larger than a size of a die which may be connected to a contact pad above the metal layer within the area. A dam may comprise a conductive material, or a non-conductive material, or both. An underfill may be formed under the die, above the metal layer, and contained within the area surrounded by the dam, so that no underfill may overflow outside the area surrounded by the dam. Additional package may be placed above the die connected to the interposer to form a package-on-package structure.

Abstract translation: 插入件可以包括衬底上方的金属层。 可以在金属层上方形成坝或多个堤坝。 大坝围绕尺寸大于模具尺寸的区域，该区域可以连接到该区域内的金属层上方的接触垫。 大坝可以包括导电材料或非导电材料，或两者。 可以在模具下方形成底部填充物，在金属层之上，并且包含在由坝围绕的区域内，使得底部填充物不会溢出到由坝围绕的区域外部。 附加封装可以放置在与插入件连接的管芯上方以形成封装封装结构。

公开(公告)号：US20170034925A1

公开(公告)日：2017-02-02

申请号：US15289950

申请日：2016-10-10

Applicant: Unimicron Technology Corp.

Inventor： Yin-Ju CHEN ,  Ming-Hao WU ,  Cheng-Po YU

IPC: H05K3/46 ,  H05K3/30 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H01L35/30 ,  H05K3/36 ,  H05K3/40 ,  H05K1/02

CPC classification number: H05K3/4647 ,  G06F1/206 ,  H01L23/12 ,  H01L23/13 ,  H01L23/4275 ,  H01L23/49827 ,  H01L35/30 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15153 ,  H01L2924/15313 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/113 ,  H05K1/14 ,  H05K1/181 ,  H05K1/185 ,  H05K1/187 ,  H05K3/36 ,  H05K3/4697 ,  H05K2201/048 ,  H05K2201/10219 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734

Abstract: A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.

Abstract translation: 具有热恢复功能的电路板包括基板，储热装置和热电装置。 储热装置嵌入在基板中并与处理器连接，以与处理器进行热交换。 嵌入在基板中的热电装置包括第一金属结表面和第二金属结表面。 第一金属接合面与蓄热装置连接，与蓄热装置进行热交换。 第二金属结表面与第一金属结表面接合，其中热电装置通过第一金属接合表面和第二金属结表面之间的温度差产生电位。