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    Method of manufacturing mounting substrate on which monolithic ceramic capacitors are mounted and mounting structure
    41.
    发明授权
    Method of manufacturing mounting substrate on which monolithic ceramic capacitors are mounted and mounting structure 有权
    制造安装有单片陶瓷电容器的安装基板的制造方法和安装结构

    公开(公告)号：US09338889B2

    公开(公告)日：2016-05-10

    申请号：US14050842

    申请日：2013-10-10

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Kazuo Hattori ,  Isamu Fujimoto ,  Norio Shiroiwa

    IPC: H05K1/18 ,  H05K3/30 ,  H01G4/30 ,  H05K1/11 ,  H05K3/34 ,  H01G2/06 ,  H01G4/232

    CPC classification number: H05K1/181 ,  H01G2/065 ,  H01G4/232 ,  H01G4/30 ,  H05K1/111 ,  H05K3/303 ,  H05K3/3415 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/10545 ,  H05K2201/2045 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913

    Abstract: A method of manufacturing a mounting substrate in which a pair of monolithic ceramic capacitors each of which includes a multilayer body in which a plurality of dielectric ceramic sheets and a plurality of substantially planar inner electrodes are stacked on top of one another and at least a pair of outer electrodes electrically connected to the inner electrodes and provided on a surface of the multilayer body are mounted on a circuit board includes a process of joining the outer electrodes to lands formed on the front rear surfaces of the circuit board, the lands formed on the front surface being formed at positions that are plane-symmetrical to positions of the corresponding lands formed on the rear surface while being electrically connected to the corresponding lands formed on the rear surface, such that surface directions of planes of the inner electrodes match each other.

    Abstract translation: 一种制造安装基板的方法，其中，一对叠层陶瓷电容器包括多层体，其中多个介电陶瓷片和多个基本上平面的内电极彼此堆叠并且至少一对 电连接到内部电极并设置在多层体的表面上的外部电极安装在电路板上，包括将外部电极连接到形成在电路板的前后表面上的平台， 前表面形成在与形成在后表面上的相应焊盘的位置平面对称的位置处，同时电连接到形成在后表面上的相应焊盘，使得内电极的平面的表面方向彼此匹配。

    Blind Via Printed Circuit Board Fabrication Supporting Press Fit Connectors
    42.
    发明申请
    Blind Via Printed Circuit Board Fabrication Supporting Press Fit Connectors 审中-公开
    盲孔通过印刷电路板制造支撑压配合连接器

    公开(公告)号：US20160050756A1

    公开(公告)日：2016-02-18

    申请号：US14886790

    申请日：2015-10-19

    Applicant: Dell Products L.P.

    Inventor： Kevin W. Mundt ,  Jason D. Adrian

    IPC: H05K1/11 ,  H05K3/42 ,  H05K3/36 ,  H01R12/70 ,  H05K3/00

    CPC classification number: H05K1/115 ,  H01R12/585 ,  H05K3/0047 ,  H05K3/0094 ,  H05K3/306 ,  H05K3/421 ,  H05K3/4611 ,  H05K2201/09509 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2203/1476 ,  Y10T29/49126

    Abstract: An information handling system circuit board interfaces storage device surface connectors and storage device controllers disposed on opposing sides by coupling a first circuit board portion having a controller press in connector to a second circuit board portion having plural surface connectors. The first and second circuit board portions couple to each other with an adhesive activated by curing. Resistant ink is printed over openings of the first circuit board portion where adhesive is applied in order to prevent the adhesive from flowing into the openings at or before the curing of the adhesive.

    Abstract translation: 信息处理系统电路板通过将具有连接器中的控制器压力的第一电路板部分耦合到具有多个表面连接器的第二电路板部分，将设置在相对侧上的存储装置表面连接器和存储装置控制器接合。 第一和第二电路板部分通过固化而激活的粘合剂彼此连接。 在第一电路板部分的开口上印刷耐油墨，其中施加粘合剂以防止粘合剂在粘合剂固化期间或之前流入开口。

    PROXIMITY SENSOR MODULE INCLUDING TIME-OF-FLIGHT SENSOR
    44.
    发明申请
    PROXIMITY SENSOR MODULE INCLUDING TIME-OF-FLIGHT SENSOR 有权
    接近传感器模块，包括飞行时间传感器

    公开(公告)号：US20160025855A1

    公开(公告)日：2016-01-28

    申请号：US14806770

    申请日：2015-07-23

    Applicant: Heptagon Micro Optics Pte. Ltd.

    Inventor： Camilla Camarri ,  Jonathan Hobbis ,  Bassam Hallal

    IPC: G01S17/02 ,  G01S7/481 ,  H05K3/30 ,  G01S17/08

    CPC classification number: G01S17/026 ,  G01S7/4813 ,  G01S7/4816 ,  G01S7/497 ,  G01S17/08 ,  G01S2007/4975 ,  H05K1/0274 ,  H05K1/181 ,  H05K1/183 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2201/10545

    Abstract: The present disclosure describes proximity sensor modules that include a time-of-flight (TOF) sensor. The module can include a plurality of chambers corresponding, respectively, to a light emission channel and a light detection channel. The channels can be optically separated from one another such that light from a light emitter element in the light emission chamber does not impinge directly on light sensitive elements of the TOF sensor in the light detection chamber. To achieve a module with a relatively small footprint, some parts of the TOF sensor can be located within the light emission chamber.

    Abstract translation: 本公开描述了包括飞行时间（TOF）传感器的接近传感器模块。 模块可以包括分别对应于发光通道和光检测通道的多个室。 通道可以彼此光学地分离，使得来自发光室中的发光元件的光不直接照射在光检测室中的TOF传感器的光敏元件上。 为了实现占地面积相对较小的模块，TOF传感器的一些部件可以位于发光室内。

    METHOD AND SYSTEM FOR REDUCING AUDIBLE AND/OR ELECTRICAL NOISE FROM ELECTRICALLY OR MECHANICALLY EXCITED CAPACITORS
    47.
    发明申请
    METHOD AND SYSTEM FOR REDUCING AUDIBLE AND/OR ELECTRICAL NOISE FROM ELECTRICALLY OR MECHANICALLY EXCITED CAPACITORS 审中-公开
    用于从电动或机械式电动机减少可听和/或电气噪声的方法和系统

    公开(公告)号：US20150228410A1

    公开(公告)日：2015-08-13

    申请号：US14694437

    申请日：2015-04-23

    Applicant: ALLISON TRANSMISSION, INC.

    Inventor： Steven D. Slagle ,  James D. Shaw ,  George C. Mimms ,  Kyle E. Erickson

    IPC: H01G4/35 ,  H01G2/06 ,  H01G4/12 ,  H01G4/38 ,  H05K1/18 ,  H01G4/30

    CPC classification number: H01G4/35 ,  F16H57/0006 ,  H01G2/065 ,  H01G4/12 ,  H01G4/30 ,  H01G4/38 ,  H01G4/40 ,  H05K1/0231 ,  H05K1/18 ,  H05K1/181 ,  H05K3/30 ,  H05K2201/10015 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/2045 ,  H05K2203/1572 ,  Y02P70/611 ,  Y10T29/4913

    Abstract: Devices and methods are disclosed for reducing vibration and noise from capacitor devices. The device includes a circuit board, and first and second capacitor structures. The second capacitor structure has substantially the same properties as the first and is coupled to the opposite face of a supporting structure substantially opposite of the first capacitor structure. The first and second capacitor structures can receive substantially the same excitation signals, can be electrically connected in parallel or in series. The first and second capacitor structures can be discrete capacitors, capacitor layers, stacks or arrays of multiple capacitor devices, or other capacitor structures. Stacks of multiple capacitor devices can be arranged symmetrically about the supporting structure. Arrays of multiple capacitor devices can be arranged with offsetting capacitors on the opposite face of the supporting structure substantially opposite one another.

    Abstract translation: 公开了用于减少电容器装置的振动和噪声的装置和方法。 该装置包括电路板，以及第一和第二电容器结构。 第二电容器结构具有与第一电容器结构基本上相同的特性，并且耦合到与第一电容器结构基本相反的支撑结构的相对面。 第一和第二电容器结构可以接收基本上相同的激励信号，可以并联或串联电连接。 第一和第二电容器结构可以是分立电容器，电容器层，堆叠或多个电容器器件的阵列，或其它电容器结构。 可以围绕支撑结构对称地布置多个电容器装置的堆叠。 多个电容器器件的阵列可以在支撑结构的相对面上大致相反地布置有抵消电容器。

    Connection substrate
    48.
    发明授权
    Connection substrate 有权
    连接基板

    公开(公告)号：US09000388B2

    公开(公告)日：2015-04-07

    申请号：US13640395

    申请日：2011-01-27

    Applicant: Fumiyuki Tokura ,  Mitsutoshi Sugiya ,  Shigeru Suzuki ,  Takashi Tonbe

    Inventor： Fumiyuki Tokura ,  Mitsutoshi Sugiya ,  Shigeru Suzuki ,  Takashi Tonbe

    IPC: G01T1/20 ,  H01R13/02 ,  H01R13/46 ,  H01L27/146 ,  H05K1/02 ,  H05K1/11

    CPC classification number: G01T1/2018 ,  H01L27/14623 ,  H01L27/14634 ,  H01L27/14661 ,  H01L27/14663 ,  H05K1/0218 ,  H05K1/0242 ,  H05K1/025 ,  H05K1/113 ,  H05K2201/09727 ,  H05K2201/10545 ,  H05K2201/10674

    Abstract: A connection substrate 13 includes a base material 130 formed by stacking a plurality of dielectric layers 130a to 130f and a plurality of through conductors 20 provided penetrating through the dielectric layers 130c to 130f adjacent to each other. A plurality of radiation shielding films 21a to 23a formed integrally with each of the plurality of through conductors 20 and separated from each other are provided at two or more interlayer parts in the dielectric layers 130c to 130f. A region PR1 of the radiation shielding film 21a (21b) formed integrally with one through conductor 20 in one interlayer part projected onto a virtual plane normal to a predetermined direction and a region of the radiation shielding film 22b or 22c (22c) formed integrally with another through conductor 20 in another interlayer part projected onto the virtual plane do not overlap each other. Accordingly, the readout circuits of an integrated circuit device can be protected from radiation, and an increase in parasitic capacitance can be suppressed.

    Abstract translation: 连接基板13包括通过堆叠多个电介质层130a至130f而形成的基底材料130和穿过彼此相邻的电介质层130c至130f设置的多个贯穿导体20。 在电介质层130c〜130f的两个以上的层间部分设置有与多个贯通导体20中的每一个一体地形成并彼此分离的多个辐射屏蔽膜21a至23a。 辐射屏蔽膜21a（21b）的区域PR1与一个中间部分中的一个贯通导体20一体地形成，该层间部分投射到垂直于预定方向的虚拟平面上，并且辐射屏蔽膜22b或22c（22c）的区域与 投影到虚拟平面上的另一层间部分中的另一贯穿导体20彼此不重叠。 因此，集成电路器件的读出电路可以被保护免受辐射，并且可以抑制寄生电容的增加。

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