公开(公告)号：US20090079274A1

公开(公告)日：2009-03-26

申请号：US11858663

申请日：2007-09-20

Applicant: Moises Cases ,  Byron L. Krauter ,  Bhyrav M. Mutnury ,  Nam H. Pham

Inventor： Moises Cases ,  Byron L. Krauter ,  Bhyrav M. Mutnury ,  Nam H. Pham

IPC: H02B1/20 ,  H01B7/30 ,  H01R12/16

CPC classification number: H01P1/047 ,  H01R13/6464 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0262 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/10189

Abstract: In electronic devices with signal traces positioned between a ground layer and a voltage reference layer, systems and methods are provided for connecting a hot pluggable device to the electronic device in a manner that diminishes signal degradation due to parasitic effects. The first device has a second reference layer near the connector that connects to a second device voltage reference layer maintained at a given voltage level across the connector. In the first device near the connector the signal trace is positioned in between a ground layer of the first device and the second reference layer which is maintained at a given voltage by a voltage regulator of the second device. The signal return current travels past the second reference layer to a first reference layer of the first device which is maintained by the first device's voltage regulator through AC decoupling capacitors minimizing the current return path discontinuity.

Abstract translation: 在具有位于接地层和电压参考层之间的信号迹线的电子设备中，提供了用于以可减少由于寄生效应引起的信号劣化的方式将热可插拔设备连接到电子设备的系统和方法。 第一设备具有连接器附近的第二参考层，其连接到跨连接器保持在给定电压电平的第二设备电压参考层。 在连接器附近的第一器件中，信号迹线位于第一器件的接地层和由第二器件的电压调节器保持在给定电压之间的第二参考层之间。 信号返回电流经过第二参考层行进到第一器件的第一参考层，该第一参考层由第一器件的电压调节器通过AC去耦电容器维持，使电流返回路径不连续性最小化。

公开(公告)号：US07491896B2

公开(公告)日：2009-02-17

申请号：US12010004

申请日：2008-01-18

Applicant: John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

Inventor： John M. Lauffer ,  James M. Larnerd ,  Voya R. Markovich

IPC: H05K1/11

CPC classification number: H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0256 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4641 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09481 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49176 ,  H01L2224/0401

Abstract: An information handling system, e.g., a mainframe computer, which includes as part thereof a housing having therein an electrical assembly including a circuitized substrate which in turn includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within the system. At least one electrical component is positioned on and electrically coupled to the circuitized substrate of the system's electrical assembly.

Abstract translation: 一种信息处理系统，例如主机计算机，其包括作为其一部分的壳体，其中具有包括电路化基板的电组件，该电组件又包括多个邻接的开放段，其限定导电层内的相对边缘部分，以隔离单独的 导电层的部分，使得该层可用于不同的功能，例如作为系统内的功率和接地元件。 至少一个电气部件位于系统的电气组件的电路化基板上并电耦合到电路基板。

公开(公告)号：US07449969B2

公开(公告)日：2008-11-11

申请号：US11309629

申请日：2006-09-01

Applicant: Hai-Yun Zhang

Inventor： Hai-Yun Zhang

IPC: H03B5/32 ,  H03B5/36 ,  H03L1/00

CPC classification number: H05K1/0243 ,  H05K1/0231 ,  H05K3/3447 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10075 ,  H05K2201/10689

Abstract: A printed circuit board (PCB) includes a signal layer and a power layer. The signal layer includes a crystal oscillator pad, a clock generator pad, and two capacitor pads. The crystal oscillator pad is connected to the clock generator pad and the capacitor pads via two signal lines. The power layer is divided into two areas by a cut-off line, the two areas respectively having different voltages. The cut-off line is located at one side of the crystal oscillator pad and the clock generator pad.

Abstract translation: 印刷电路板（PCB）包括信号层和功率层。 信号层包括晶体振荡器垫，时钟发生器垫和两个电容器垫。 晶体振荡器垫通过两条信号线连接到时钟发生器焊盘和电容器焊盘。 功率层通过截止线分成两个区域，两个区域分别具有不同的电压。 切断线位于晶体振荡器垫的一侧和时钟发生器垫。

公开(公告)号：US07447038B2

公开(公告)日：2008-11-04

申请号：US11304625

申请日：2005-12-16

Applicant: Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba

Inventor： Yutaka Uematsu ,  Hideki Osaka ,  Yoji Nishio ,  Seiji Funaba

IPC: H05K1/00

CPC classification number: H05K1/023 ,  H01L23/50 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48195 ,  H01L2224/48472 ,  H01L2224/49 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0227 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10545 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.

Abstract translation: 在存储器模块中，多个存储器安装在模块基板上，每个存储器附近的Vref和Vss之间的阻抗通过去耦电容器和Vref平面耦合到Vss，以在宽的频率范围内实现低阻抗配置，Vref平面 分别提供给各个存储器，并且Vref平面通过使用高阻抗线或高阻抗芯片部分彼此连接。 因此，可以提供一种能够有效降低自身噪声和传播噪声的用于模块的布线技术。

公开(公告)号：US07438560B2

公开(公告)日：2008-10-21

申请号：US11840709

申请日：2007-08-17

Applicant: Yasuhiro Takahashi

Inventor： Yasuhiro Takahashi

IPC: H01R12/00

CPC classification number: H05K1/0216 ,  H05K1/023 ,  H05K1/0237 ,  H05K1/0239 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09972

Abstract: A printed wiring board, comprising a signal plane having a baseband block for processing a baseband signal and a high-frequency block for processing a high-frequency signal which is obtained by converting the baseband signal, and a ground plane opposing to the signal plane. The baseband block and the high-frequency block are connected through a transmission line for transmitting a signal of a specific frequency region. The ground plane is provided with a first ground portion and a second ground portion, the first ground portion being provided at an area opposing to the baseband block, the second ground portion being provided at an area opposing to the high-frequency block. The first ground portion and the second ground portion are coupled to each other through a coupling portion provided therebetween which has a low impedance with respect to the signal of the specific frequency region.

Abstract translation: 一种印刷电路板，包括具有用于处理基带信号的基带块的信号平面和用于处理通过转换基带信号而获得的高频信号的高频块以及与信号面相对的接地面。 基带块和高频块通过用于发送特定频率区域的信号的传输线路连接。 接地平面设置有第一接地部分和第二接地部分，第一接地部分设置在与基带部件相对的区域处，第二接地部分设置在与高频部件相对的区域。 第一接地部分和第二接地部分通过设置在它们之间的耦合部分彼此耦合，其相对于特定频率区域的信号具有低阻抗。

公开(公告)号：US20080217049A1

公开(公告)日：2008-09-11

申请号：US12045660

申请日：2008-03-10

Applicant: George Dudnikov

Inventor： George Dudnikov

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01G4/06 ,  H01G4/30 ,  H01G4/306 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/18 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0355 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09663 ,  H05K2203/162 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

公开(公告)号：US20080214136A1

公开(公告)日：2008-09-04

申请号：US12121828

申请日：2008-05-16

Applicant: Gerard James Hayes ,  Scott Ladell Vance

Inventor： Gerard James Hayes ,  Scott Ladell Vance

IPC: H04B1/10

CPC classification number: H05K9/0039 ,  H04B1/3838 ,  H05K1/0216 ,  H05K1/0224 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/167 ,  H05K2201/093 ,  H05K2201/09354 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/10446

Abstract: The present invention uses metallization termination techniques to reduce the electro-magnetic field scattering at the edges of metallized areas. The metallization termination techniques provide a gradual transition from high conductivity areas to high impedance areas. The mobile phone antenna illuminates the PCB allowing currents to flow on the PCB. When the currents reach edges of the PCB they flow through a region of increasingly high impedance without reflecting back or scattering.

公开(公告)号：US07361994B2

公开(公告)日：2008-04-22

申请号：US11239952

申请日：2005-09-30

Applicant: Xiaoning Ye

Inventor： Xiaoning Ye

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/645 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: A system may include a conductive plane defining a non-conductive antipad area and a second non-conductive area extending from the antipad area in at least a first direction, a dielectric plane coupled to the conductive plane, a conductive via passing through the dielectric plane and the antipad area, a conductive pad connected to an end of the conductive via, and a conductive trace coupled to the dielectric plane and connected to the conductive pad, the conductive trace extending from the conductive pad in the first direction.

Abstract translation: 系统可以包括限定非导电止动区域的导电平面和在至少第一方向上从止血区域延伸的第二非导电区域，耦合到导电平面的电介质平面，穿过电介质平面的导电通孔 并且所述反面区域，连接到所述导电通孔的端部的导电焊盘以及耦合到所述电介质平面并连接到所述导电焊盘的导电迹线，所述导电迹线从所述导电焊盘沿所述第一方向延伸。

公开(公告)号：US07361843B2

公开(公告)日：2008-04-22

申请号：US11236960

申请日：2005-09-28

Applicant: Ernest Lentschke ,  Jeffrey C. Hailey ,  Raymond McCormick

Inventor： Ernest Lentschke ,  Jeffrey C. Hailey ,  Raymond McCormick

IPC: H05K1/03

CPC classification number: H05K1/0231 ,  H05K1/0227 ,  H05K1/162 ,  H05K2201/0209 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09881 ,  Y10T29/4913

Abstract: An information handling system has a printed circuit board with a split power plane having a plurality of sections that may be used for distributing different voltages on a single conductive foil layer of the printed circuit board to components on the printed circuit board. Capacitive coupling of the split power plane sections may be enhanced with a high dielectric fill between the portions.

Abstract translation: 信息处理系统具有印刷电路板，其具有分割电源平面，具有多个部分，该多个部分可用于将印刷电路板的单个导电箔层上的不同电压分配到印刷电路板上的组件。 分开的功率平面部分的电容耦合可以通过部分之间的高电介质填充来增强。

公开(公告)号：US20080059919A1

公开(公告)日：2008-03-06

申请号：US11936673

申请日：2007-11-07

Applicant: Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

Inventor： Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

IPC: G06F17/50

CPC classification number: H05K1/0265 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10189 ,  Y10T29/49156

Abstract: A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract translation: 用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。 在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。 连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。 槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。 所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。