公开(公告)号：US20180342422A1

公开(公告)日：2018-11-29

申请号：US15606456

申请日：2017-05-26

Applicant: APPLIED MATERIALS, INC.

Inventor： Wenguang Li ,  James S. Papanu ,  Wei-Sheng Lei ,  Prabhat Kumar ,  Brad Eaton ,  Ajay Kumar ,  Alexander N. Lerner

IPC: H01L21/78 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/268 ,  H01L21/02

Abstract: Light-absorbing masks and methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits involves forming a mask above the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light-absorber species throughout the water-soluble matrix. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask with gaps and corresponding trenches in the semiconductor wafer in regions between the integrated circuits. The semiconductor wafer is plasma etched through the gaps in the patterned mask to extend the trenches and to singulate the integrated circuits. The patterned mask protects the integrated circuits during the plasma etching.

公开(公告)号：US09911582B2

公开(公告)日：2018-03-06

申请号：US14939787

申请日：2015-11-12

Applicant: Applied Materials, Inc.

Inventor： Banqiu Wu ,  Ajay Kumar ,  Kartik Ramaswamy ,  Omkaram Nalamasu

IPC: H01J37/32 ,  H01L21/027 ,  H01L21/311

CPC classification number: H01J37/32669 ,  H01J37/32009 ,  H01J37/32422 ,  H01J37/3244 ,  H01L21/0273 ,  H01L21/31144

Abstract: The present disclosure provides methods and an apparatus for controlling and modifying line width roughness (LWR) of a photoresist layer with enhanced electron spinning control. In one embodiment, an apparatus for controlling a line width roughness of a photoresist layer disposed on a substrate includes a processing chamber having a chamber body having a top wall, side wall and a bottom wall defining an interior processing region, a support pedestal disposed in the interior processing region of the processing chamber, and a plasma generator source disposed in the processing chamber operable to provide predominantly an electron beam source to the interior processing region.

公开(公告)号：US09793132B1

公开(公告)日：2017-10-17

申请号：US15154790

申请日：2016-05-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Wenguang Li ,  James S. Papanu ,  Ramesh Krishnamurthy ,  Prabhat Kumar ,  Brad Eaton ,  Ajay Kumar ,  Alexander N. Lerner

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/78 ,  H01L21/3065

CPC classification number: H01L21/3086 ,  H01L21/02057 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/78

Abstract: Etch masks and methods of dicing semiconductor wafers are described. In an example, an etch mask for a wafer singulation process includes a water-soluble matrix based on a solid component and water. The etch mask also includes a plurality of particles dispersed throughout the water-soluble matrix. The plurality of particles has an average diameter approximately in the range of 5-100 nanometers. A ratio of weight % of the solid component to weight % of the plurality of particles is approximately in the range of 1:0.1-1:4.

公开(公告)号：US09721839B2

公开(公告)日：2017-08-01

申请号：US14738389

申请日：2015-06-12

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Mohammad Kamruzzaman Chowdhury ,  Brad Eaton ,  Ajay Kumar

IPC: H01L21/02 ,  H01L21/82 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/67 ,  H01J37/32

CPC classification number: H01L21/82 ,  H01J37/32889 ,  H01J37/32899 ,  H01J2237/334 ,  H01J2237/335 ,  H01L21/02057 ,  H01L21/02076 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31127 ,  H01L21/32131 ,  H01L21/67207 ,  H01L21/78

Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a water soluble mask above the semiconductor wafer, the water soluble mask covering and protecting the integrated circuits. The method also includes baking the water soluble mask to increase the etch resistance of the water soluble mask. The method also includes, subsequent to baking the water soluble mask, patterning the water soluble mask with a laser scribing process to provide a water soluble patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes plasma etching the semiconductor wafer through the gaps in the water soluble patterned mask to singulate the integrated circuits.

公开(公告)号：US09252057B2

公开(公告)日：2016-02-02

申请号：US14052085

申请日：2013-10-11

Applicant: APPLIED MATERIALS, INC.

Inventor： Mohammad Kamruzzaman Chowdhury ,  Wei-Sheng Lei ,  Todd Egan ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC: H01L21/82 ,  H01L21/67 ,  H01L21/78 ,  H01L21/683

CPC classification number: H01L21/82 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: Methods and systems of laser and plasma etch wafer dicing using UV-curable adhesive films. A method includes forming a mask covering ICs formed on the wafer. The semiconductor wafer is coupled to a film frame by a UV-curable adhesive film. A pre-cure of the UV-curable adhesive film cures a peripheral portion of the adhesive extending beyond an edge of the wafer to improve the exposed adhesive material's resistance to plasma etch and reduce hydrocarbon redeposition within the etch chamber. The mask is patterned by laser scribing to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer, below thin film layers from which the ICs are formed. The semiconductor wafer is plasma etched through the gaps in the patterned mask to singulate the ICs. A center portion of the UV-curable adhesive is then cured and the singulated ICs detached from the film.

Abstract translation: 使用UV固化粘合剂膜的激光和等离子体蚀刻晶片切割的方法和系统。 一种方法包括形成覆盖在晶片上形成的IC的掩模。 半导体晶片通过UV固化粘合剂膜耦合到膜框架。 紫外线固化粘合剂膜的预固化固化了延伸超过晶片边缘的粘合剂的周边部分，以改善暴露的粘合材料对等离子体蚀刻的抗性并减少蚀刻室内的烃再沉积。 通过激光划线将掩模图案化以提供具有间隙的图案化掩模。 图案化使得半导体晶片的区域在形成IC的薄膜层之下露出。 通过图案化掩模中的间隙对半导体晶片进行等离子体蚀刻，以对IC进行分离。 然后固化可UV固化粘合剂的中心部分，并将分离的IC从膜上分离出来。

公开(公告)号：US09218992B2

公开(公告)日：2015-12-22

申请号：US14166715

申请日：2014-01-28

Applicant: Applied Materials, Inc.

Inventor： Saravjeet Singh ,  Brad Eaton ,  Ajay Kumar ,  Wei-Sheng Lei ,  James M. Holden ,  Madhava Rao Yalamanchili ,  Todd J. Egan

IPC: H01L21/00 ,  H01L21/67 ,  H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/683 ,  H01L21/687 ,  B23K26/06 ,  B23K26/36 ,  B23K26/40

CPC classification number: H01L21/67069 ,  B23K26/0624 ,  B23K26/064 ,  B23K26/36 ,  B23K26/364 ,  B23K26/40 ,  B23K26/402 ,  B23K2103/172 ,  B23K2103/50 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/67092 ,  H01L21/67207 ,  H01L21/6836 ,  H01L21/68707 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2221/68377

Abstract: Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The semiconductor wafer is supported by a substrate carrier. The mask is then patterned with a laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to singulate the integrated circuits while supported by the substrate carrier.

Abstract translation: 对具有多个集成电路的各晶片的切割半导体晶片的方法和装置进行说明。 一种方法包括在半导体晶片上形成掩模，掩模由覆盖并保护集成电路的层组成。 半导体晶片由衬底载体支撑。 然后用激光划线工艺对掩模进行构图，以提供具有间隙的图案化掩模，暴露集成电路之间的半导体晶片的区域。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以在由衬底载体支撑的同时对集成电路进行分离。

公开(公告)号：US09159574B2

公开(公告)日：2015-10-13

申请号：US13973541

申请日：2013-08-22

Applicant: APPLIED MATERIALS, INC.

Inventor： Keven Yu ,  Ajay Kumar

IPC: H01L21/3065 ,  H01L21/311 ,  B81C1/00 ,  H01L21/768

CPC classification number: H01L21/3065 ,  B81C1/00619 ,  H01L21/30655 ,  H01L21/31138 ,  H01L21/76898

Abstract: Methods of silicon etch for trench sidewall smoothing are described. In one embodiment, a method involves smoothing a sidewall of a trench formed in a semiconductor wafer via plasma etching. The method includes directionally etching the semiconductor wafer with plasma generated from a fluorine gas to smooth the sidewall of the trench, the trench having a protective layer formed by plasma generated by a second process gas such as oxygen or a polymerization gas. In another embodiment, a method involves etching a semiconductor wafer to generate a trench having a smooth sidewall. The method includes plasma etching the semiconductor wafer with one or more first process gases including a fluorine gas, simultaneously performing deposition and plasma etching the semiconductor wafer with one or more second process gases including a fluorine gas and a polymerization gas mix, and performing deposition with one or more third process gases including a polymerization gas.

Abstract translation: 描述了用于沟槽侧壁平滑化的硅蚀刻方法。 在一个实施例中，一种方法包括通过等离子体蚀刻来平滑在半导体晶片中形成的沟槽的侧壁。 该方法包括使用氟气产生的等离子体对半导体晶片进行定向蚀刻，以平滑沟槽的侧壁，该沟槽具有由诸如氧气或聚合气体的第二工艺气体产生的等离子体形成的保护层。 在另一个实施例中，一种方法包括蚀刻半导体晶片以产生具有平滑侧壁的沟槽。 该方法包括使用一种或多种包括氟气的第一工艺气体对半导体晶片进行等离子体蚀刻，同时用包含氟气和聚合气体混合物的一种或多种第二工艺气体进行沉积和等离子体蚀刻半导体晶片，并且 一种或多种第三工艺气体，包括聚合气体。

公开(公告)号：US08993414B2

公开(公告)日：2015-03-31

申请号：US13938570

申请日：2013-07-10

Applicant: Applied Materials, Inc.

Inventor： Brad Eaton ,  Saravjeet Singh ,  Wei-Sheng Lei ,  Madhava Rao Yalamanchili ,  Tong Liu ,  Ajay Kumar

IPC: H01L21/78 ,  H01L21/3065

CPC classification number: H01L21/67161 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/50 ,  H01J37/32651 ,  H01J37/32788 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67742 ,  H01L21/78 ,  Y10T29/5124

Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. In embodiments, a multi-plasma etching approach is employed to dice the wafers where an isotropic etch is employed to improve the die sidewall following an anisotropic etch. The isotropic etch removes anisotropic etch byproducts, roughness, and/or scalloping from the anisotropically etched die sidewalls after die singulation.

Abstract translation: 在实施例中，实施涉及初始激光划片和随后的等离子体蚀刻的混合晶片或衬底切割工艺用于裸片切割。 激光划片工艺可用于清洁地去除掩模层，有机和无机介电层以及器件层。 然后可以在曝光或部分蚀刻晶片或衬底时终止激光蚀刻工艺。 在实施例中，采用多等离子体蚀刻方法来骰子晶片，其中采用各向同性蚀刻来改善各向异性蚀刻后的管芯侧壁。 各向同性蚀刻在单片切割之后从各向异性蚀刻的模具侧壁去除各向异性蚀刻副产物，粗糙度和/或扇贝。

公开(公告)号：US08991329B1

公开(公告)日：2015-03-31

申请号：US14169502

申请日：2014-01-31

Applicant: Applied Materials, Inc.

Inventor： Jungrae Park ,  Wei-Sheng Lei ,  Prabhat Kumar ,  James S. Papanu ,  Brad Eaton ,  Ajay Kumar

IPC: B05C11/02 ,  B05C13/02 ,  H01L21/02 ,  B05C11/08 ,  B05C13/00

CPC classification number: H01L21/02282 ,  B05B1/00 ,  B05B3/1014 ,  B05B3/1035 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/6715 ,  H01L21/6835 ,  H01L21/78 ,  H01L2221/68327

Abstract: Improved wafer coating processes, apparatuses, and systems are described. In one embodiment, an improved spin-coating process and system is used to form a mask for dicing a semiconductor wafer with a laser plasma dicing process. In one embodiment, a spin-coating apparatus for forming a film over a semiconductor wafer includes a rotatable stage configured to support the semiconductor wafer. The rotatable stage has a downward sloping region positioned beyond a perimeter of the semiconductor wafer. The apparatus includes a nozzle positioned above the rotatable stage and configured to dispense a liquid over the semiconductor wafer. The apparatus also includes a motor configured to rotate the rotatable stage.

Abstract translation: 描述了改进的晶片涂布工艺，装置和系统。 在一个实施例中，改进的旋涂工艺和系统用于形成用激光等离子体切割工艺切割半导体晶片的掩模。 在一个实施例中，用于在半导体晶片上形成膜的旋涂装置包括被配置为支撑半导体晶片的可旋转台。 可旋转台具有位于半导体晶片周边之外的向下倾斜区域。 该设备包括位于可旋转台上方并被配置为在半导体晶片上分配液体的喷嘴。 该装置还包括构造成旋转可旋转台的马达。

公开(公告)号：US08946057B2

公开(公告)日：2015-02-03

申请号：US13847964

申请日：2013-03-20

Applicant: Applied Materials, Inc.

Inventor： Wei-Sheng Lei ,  Mohammad K. Chowdhury ,  Todd Egan ,  Brad Eaton ,  Madhava Rao Yalamanchili ,  Ajay Kumar

IPC: H01L21/00 ,  H01L21/78 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/67069 ,  H01L21/67207

Abstract: Laser and plasma etch wafer dicing using UV-curable adhesive films is described. In an example, a method includes forming a mask above the semiconductor wafer. The semiconductor wafer is coupled to a carrier substrate by a UV-curable adhesive film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The UV-curable adhesive film is then irradiated with ultra-violet (UV) light. The singulated integrated circuits are then detached from the carrier substrate.

Abstract translation: 描述了使用UV固化粘合剂膜的激光和等离子体蚀刻晶片切割。 在一个示例中，一种方法包括在半导体晶片上形成掩模。 半导体晶片通过UV可固化粘合剂膜耦合到载体衬底。 面罩覆盖并保护集成电路。 用激光划线工艺对掩模进行图案化以提供具有间隙的图案化掩模。 图案化使得集成电路之间的半导体晶片的区域露出。 然后通过图案化掩模中的间隙蚀刻半导体晶片，以形成单独的集成电路。 然后用紫外线（UV）光照射UV固化粘合剂膜。 然后将分离的集成电路从载体衬底分离。