公开(公告)号：US20070248800A1

公开(公告)日：2007-10-25

申请号：US11785794

申请日：2007-04-20

Applicant: Chihiro Mitsui ,  Chikara Shimada

Inventor： Chihiro Mitsui ,  Chikara Shimada

IPC: B32B3/00

CPC classification number: H05K1/0269 ,  H05K3/4638 ,  H05K2201/09327 ,  H05K2201/09781 ,  H05K2201/09909 ,  Y10T428/24917

Abstract: The invention provides a layer configuration indicator portion enabling the configuration of layers to be identified easily in a multilayer board. The configuration of the respective layers of a multilayer board can be identified easily by applying two copper foils per a single layer for a number corresponding to the number of layers constituting the multilayer board on an outer layer of the multilayer board, by which layer configuration identification marks are composed, and displaying a maximum of six types of configurations per each layer by having three types of statuses indicated on the layer configuration indication marks, which are “covering the mark with resist”, “covering the mark with resist and silk”, and “not covering the mark with resist or silk”.

Abstract translation: 本发明提供一种能够在多层板中容易地识别层的配置的层配置指示器部分。 可以容易地识别多层板的各层的构造，通过在多层板的外层上，对应于构成多层板的层数，每单层涂敷两层铜箔，层构造识别 通过在层“配置指示标记”上指示的三种类型的状态，即“用抗蚀剂覆盖标记”，“用抗蚀剂和丝绸覆盖标记”来表示每层最多显示六种配置， 和“不用抗拒或丝绸覆盖的标记”。

公开(公告)号：US07237587B2

公开(公告)日：2007-07-03

申请号：US11244333

申请日：2005-10-06

Applicant: Sung-ki Kim

Inventor： Sung-ki Kim

IPC: H01K1/03

CPC classification number: H05K1/0216 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09327

Abstract: A multi-layer PCB includes a first signal layer, a ground layer, a second signal layer, a third signal layer, an electric power layer, and a fourth signal layer, including a first insulating layer arranged between the first signal layer and the ground layer; a second insulating layer arranged between the ground layer and the second signal layer; a third insulating layer arranged between the second signal layer and the third signal layer; a fourth insulating layer arranged between the third signal layer and the electric power layer; and a fifth insulating layer arranged between the electric power layer and the fourth signal layer, wherein at least one of the first signal layer, the second signal layer, the third signal layer, and the fourth signal layer includes a pattern.

Abstract translation: 多层PCB包括第一信号层，接地层，第二信号层，第三信号层，电力层和第四信号层，包括布置在第一信号层和地之间的第一绝缘层 层; 布置在所述接地层和所述第二信号层之间的第二绝缘层; 布置在所述第二信号层和所述第三信号层之间的第三绝缘层; 布置在所述第三信号层和所述电力层之间的第四绝缘层; 以及布置在所述电力层和所述第四信号层之间的第五绝缘层，其中所述第一信号层，所述第二信号层，所述第三信号层和所述第四信号层中的至少一个包括图案。

公开(公告)号：US07124502B2

公开(公告)日：2006-10-24

申请号：US10917553

申请日：2004-08-11

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01K3/22

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

公开(公告)号：US06744130B1

公开(公告)日：2004-06-01

申请号：US10615063

申请日：2003-07-08

Applicant: Leah M. Miller ,  Aritharan Thurairajaratnam ,  Edwin M. Fulcher

Inventor： Leah M. Miller ,  Aritharan Thurairajaratnam ,  Edwin M. Fulcher

IPC: H01L2348

CPC classification number: H05K1/0245 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/16 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: A package substrate having separate routing layers for transmitter signals and receiver signals, which signals are routed in differential pairs. The differential pairs of signal routing lines are isolated between a separate ground plane for transmitter and receiver traces and dedicated power planes, where a single power plane is dedicated to a single differential pair of signal routing lines. In this manner, a high degree of electrical isolation exists not only between the transmitter signal traces and the receiver signal traces, which are on different layers, but also between different differential pairs of signal routing lines on the same layer, each of which has its own dedicated power plane. Thus, a very high speed core routing system can be designed in a package substrate that can then be adapted as necessary to support a broad range of different integrated circuit designs.

Abstract translation: 封装衬底具有用于发射机信号和接收机信号的分离的路由层，哪些信号以差分对路由。 信号路由线路的差分对在用于发射器和接收器迹线的独立接地平面和专用功率平面之间隔离，其中单个功率平面专用于单个差分信号路由线路对。 以这种方式，高度的电隔离不仅存在于发射机信号迹线和位于不同层上的接收机信号迹线之间，而且存在于同一层上的信号路由线路的不同差分对之间， 自有专用电源机。 因此，可以在封装衬底中设计非常高速的芯路由系统，然后可以根据需要进行调整，以支持各种不同的集成电路设计。

公开(公告)号：US06548858B2

公开(公告)日：2003-04-15

申请号：US09800409

申请日：2001-03-06

Applicant: Yu-Chiang Cheng

Inventor： Yu-Chiang Cheng

IPC: H01L29792

CPC classification number: H05K1/024 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/09327 ,  Y10T29/49126

Abstract: A multi-layer circuit board includes first, second, third, fourth and fifth insulating substrates, first, second, third and fourth signal wiring layers, a ground wiring layer and a power wiring layer. The insulating substrates and the wiring layers are press-bonded to each other to form the circuit board with a thickness of about 1.0 mm. Each of the first and fifth insulating substrates has a thickness ranging from 5.225 to 5.775 mil. Each of the second and fourth insulating substrates has a thickness ranging from 7.6 to 8.4 mil. The third insulating substrate has a thickness ranging from 3.8 to 4.2 mil. The first signal wiring layer has a first resistance with respect to the ground wiring layer. The second signal wiring layer has a second resistance with respect to the ground wiring layer and the power wiring layer. The third signal wiring layer has a third resistance with respect to the ground wiring layer and the power wiring layer. The fourth signal wiring layer has a fourth resistance with respect to the power wiring layer. The first, second, third and fourth resistances are within the range of 49.5 to 60.5 ohms.

公开(公告)号：US06378201B1

公开(公告)日：2002-04-30

申请号：US08497614

申请日：1995-06-30

Applicant: Yutaka Tsukada ,  Shuhei Tsuchida

Inventor： Yutaka Tsukada ,  Shuhei Tsuchida

IPC: H01K310

CPC classification number: H05K3/4602 ,  H05K1/0265 ,  H05K3/0023 ,  H05K3/181 ,  H05K3/426 ,  H05K3/429 ,  H05K3/4661 ,  H05K2201/0352 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2203/1438 ,  H05K2203/1581 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer printed circuit board and a corresponding fabrication method are disclosed, which circuit board achieves a relatively high degree of wiring density and a relatively high degree of wiring design freedom. These advantages are obtained in the inventive printed circuit board by electrically connecting power conductors or ground conductors using through holes. On the other hand, signal conductors in any two adjacent signal wiring layers are electrically connected using via holes extending only through an intervening electrically insulating layer. Preferably, the electrically insulating layer is a layer of photosensitive resin and the via holes are formed using conventional photolithographic techniques.

Abstract translation: 公开了一种多层印刷电路板和相应的制造方法，该电路板实现相对高的布线密度和相对高的布线设计自由度。 通过使用通孔电连接电源导体或接地导体，在本发明的印刷电路板中获得这些优点。 另一方面，任何两个相邻信号布线层中的信号导体使用仅通过中间电绝缘层延伸的通孔电连接。 优选地，电绝缘层是感光树脂层，并且通孔使用常规的光刻技术形成。

公开(公告)号：US06181004B2

公开(公告)日：2001-01-30

申请号：US09235982

申请日：1999-01-22

Applicant: Jerry D. Koontz ,  Donald F. Coffin

Inventor： Jerry D. Koontz ,  Donald F. Coffin

IPC: H01L2352

CPC classification number: H05K1/0268 ,  H01L2224/16225 ,  H05K1/0216 ,  H05K1/0262 ,  H05K1/112 ,  H05K2201/09227 ,  H05K2201/09327 ,  H05K2201/10363 ,  H05K2201/10689 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: A printed circuit module supports host processors and memories. The module permits easy upgrades and repairs of the semiconductor devices without requiring modification of the motherboard. The module includes a multilayer printed circuit board with a symmetrical design, permitting chips to be placed on both sides of the board. Microvias connect the contact points on a signal layer directly to a ground layer on the printed circuit board, thereby reducing the need for escape routing. This greatly simplifies the design layout of the module, The ground layer is located between two signal layers, thereby decreasing the crosstalk between the signal layers. The symmetrical design permits drilled vias to extend from a quadrant of one chip and exit through a similar quadrant on the opposite side of the circuit board. The modular design also simplifies impedance matching. Testing of the module may also be accomplished even when the module is not fully populated through the use of test bypass circuitry.

Abstract translation: 印刷电路模块支持主处理器和存储器。 该模块允许容易地升级和修理半导体器件，而不需要修改主板。 该模块包括具有对称设计的多层印刷电路板，允许将芯片放置在电路板的两侧。 Microvias将信号层上的接触点直接连接到印刷电路板上的接地层，从而减少了逃生路由的需要。 这大大简化了模块的设计布局，地层位于两个信号层之间，从而降低了信号层之间的串扰。 对称设计允许钻孔从一个芯片的象限延伸出来并通过电路板相对侧上的类似象限出口。 模块化设计还简化了阻抗匹配。 即使模块没有通过使用测试旁路电路完全填充，也可以实现模块的测试。

公开(公告)号：US5719750A

公开(公告)日：1998-02-17

申请号：US676103

申请日：1996-07-02

Applicant: Yasushi Iwane

Inventor： Yasushi Iwane

IPC: H05K1/02 ,  H05K1/00 ,  H05K3/46 ,  H05K9/00 ,  H05K1/11 ,  H05K7/02

CPC classification number: H05K1/0216 ,  H05K1/0237 ,  H05K9/0039 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/09972 ,  H05K2201/10166

Abstract: A printed board 10 is provided with two ground layers 3a, 3b. These ground layers 3a, 3b are electrically insulated inside the printed board. By connecting circuits with different characteristics (low frequency and high frequency, for example) with the different ground layers 3a, 3b, interference of these circuits caused due to a common ground can be minimized.

Abstract translation: 印刷电路板10设置有两个接地层3a，3b。 这些接地层3a，3b在印刷电路板内电绝缘。 通过将具有不同特性（例如，低频和高频）的电路与不同的接地层3a，3b连接起来，可以最小化由于公共接地引起的这些电路的干扰。

公开(公告)号：US5378314A

公开(公告)日：1995-01-03

申请号：US77298

申请日：1993-06-15

Applicant: Walter Schmidt ,  Marco Martinelli

Inventor： Walter Schmidt ,  Marco Martinelli

IPC: C23F1/00 ,  H05K1/00 ,  H05K1/05 ,  H05K1/11 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  B44C1/22 ,  B29C37/00

CPC classification number: H05K3/42 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/4084 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652

Abstract: A method for producing aligned passages through substrate materials, in which the projection of the inlet and outlet openings does not coincide, uses displaced application of etching windows on opposite sides and corresponding pronounced under-etching of these windows. By applying displaced etching windows on both sides of the substrate and through-etching the substrate through these windows, `oblique` passages are obtained through the substrate. By a suitable location of the windows it is also possible to produce branched passages with more than one outlet opening.

Abstract translation: 用于产生通过基底材料的对准的通道的方法，其中入口和出口的突出部不重合，使用在相对侧上移动施加蚀刻窗口并且对应于这些窗口的相当明显的下蚀刻。 通过在基板的两面上施加位移蚀刻窗口，并通过这些窗口对基板进行蚀刻，通过基板获得“倾斜”通道。 通过窗口的合适位置，也可以产生具有多于一个出口开口的分支通道。

公开(公告)号：US3680005A

公开(公告)日：1972-07-25

申请号：US3680005D

申请日：1969-12-15

Applicant: BURROUGHS CORP

Inventor： JORGENSEN ARNOLD J ,  BEWLEY LAWRENCE L ,  WHITE KENNETH H

IPC: H01P3/08 ,  H02M1/00 ,  H05K1/02 ,  H05K3/40 ,  H05K3/46 ,  H01P3/02 ,  H01P3/18 ,  H05K1/04

CPC classification number: H05K3/4084 ,  H01P3/08 ,  H02M1/00 ,  H05K1/0262 ,  H05K1/0263 ,  H05K3/4092 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/0382 ,  H05K2201/044 ,  H05K2201/09327 ,  H05K2201/10303 ,  H05K2203/063

Abstract: A plurality of conductive sheets are stacked in spaced relationship. A plurality of dielectric sheets are stacked in the spaces between the conductive sheets to form with the conductive sheets an integral structure. A source of bias voltage is coupled to a first pair of the conductive sheets, a source of clock pulses is coupled to a second pair of the conductive sheets having a larger characteristic impedance than the first pair, and a source of logic levels is coupled to a third pair of the conductive sheets having a larger characteristic impedance than the second pair. The sources are coupled to their respective pairs of conductive sheets such that alternate conductive sheets are grounded. The terminal pins of circuit board connectors are selectively connected to the conductive sheets.

Abstract translation: 多个导电片以间隔的关系堆叠。 多个电介质片层叠在导电片之间的空间中，以形成具有一体结构的导电片。 偏置电压源耦合到第一对导电片，时钟脉冲源耦合到具有比第一对更大的特性阻抗的第二对导电片，并且将逻辑电平源耦合到 第三对导电片具有比第二对更大的特性阻抗。 源极耦合到它们各自的导电片对，使得交替的导电片接地。 电路板连接器的端子针选择性地连接到导电片。