公开(公告)号：US20020111050A1

公开(公告)日：2002-08-15

申请号：US09957047

申请日：2001-09-20

Inventor： Scott Parkhill ,  Sayeed Ahmed ,  Fred Flett

IPC: H05K001/00 ,  H01R012/00

CPC classification number: H05K1/0231 ,  H01L23/50 ,  H01L23/66 ,  H01L25/072 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/01039 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/0306 ,  H05K2201/09345 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/049 ,  Y02P70/611 ,  H01L2924/00

Abstract: An electrical connector for use in a power module includes a first end portion for forming an electrical connection with a substrate, a second end portion, and a compliant portion situated between the first end portion and the second end portion. The compliant portion includes a compressed position and a decompressed position. The first end portion is configured for forming an electrical connection with a substrate if the compliant portion is in the compressed position.

Abstract translation: 用于功率模块的电连接器包括用于与衬底形成电连接的第一端部，第二端部和位于第一端部和第二端部之间的柔性部分。 柔顺部分包括压缩位置和解压缩位置。 如果柔性部分处于压缩位置，则第一端部构造成用于与基底形成电连接。

公开(公告)号：US06219255B1

公开(公告)日：2001-04-17

申请号：US09137472

申请日：1998-08-20

Applicant: Abeye Teshome

Inventor： Abeye Teshome

IPC: H05K111

CPC classification number: H05K1/0253 ,  H05K1/0216 ,  H05K1/0262 ,  H05K9/0039 ,  H05K2201/09245 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/10689 ,  Y10T29/49155

Abstract: A computer system includes a microprocessor, an an input coupled to provide signal inputs to the microprocessor, a mass storage coupled to the microprocessor, a video controller for coupling the microprocessor to a display, a memory coupled to provide storage to facilitate execution of computer programs by the microprocessor, and a multilayer printed circuit board for mounting the microprocessor thereon. The multilayer printed circuit board provides for reduced electromagnetic interference (EMI) and includes at least two layers. The multilayer printed circuit board further includes a first conductive segment on a first layer, a second conductive segment on the first layer, the second segment being separated from the first segment by a primary gap, and a conductive interconnect on a second layer, the interconnect for carrying a high frequency signal therein. The second layer is disposed laterally from and substantially parallel to the first layer. The interconnect is further disposed for crossing over the first segment to the second segment in a cross-over region and wherein the first segment and the second segment are further characterized by a secondary gap in the cross-over region, the secondary gap being less than the primary gap for providing an increased coupling in the cross-over region. A method for reducing a source of EMI in a multilayer printed circuit board is also disclosed.

Abstract translation: 计算机系统包括微处理器，耦合以向微处理器提供信号输入的输入，耦合到微处理器的大容量存储器，用于将微处理器耦合到显示器的视频控制器，耦合以提供存储以便于执行计算机程序的存储器 以及用于在其上安装微处理器的多层印刷电路板。 多层印刷电路板提供降低的电磁干扰（EMI）并且包括至少两层。 所述多层印刷电路板还包括第一层上的第一导电段，所述第一层上的第二导电区段，所述第二区段通过初级间隙与所述第一区段分离，以及在第二层上的导电互连，所述互连 用于在其中携带高频信号。 第二层从第一层横向设置并基本平行于第一层。 所述互连被进一步布置成用于在交叉区域中跨越所述第一段到所述第二段，并且其中所述第一段和所述第二段的进一步特征在于所述交叉区域中的次级间隙，所述次级间隙小于 用于在交叉区域中提供增加的耦合的主要间隙。 还公开了一种用于减少多层印刷电路板中的EMI源的方法。

公开(公告)号：US06215076B1

公开(公告)日：2001-04-10

申请号：US08824798

申请日：1997-03-26

Applicant: Hideho Inagawa ,  Toru Otaki

Inventor： Hideho Inagawa ,  Toru Otaki

IPC: H01R909

CPC classification number: H05K1/0216 ,  H05K1/023 ,  H05K1/0233 ,  H05K1/0268 ,  H05K1/0286 ,  H05K3/0005 ,  H05K3/222 ,  H05K2201/086 ,  H05K2201/09236 ,  H05K2201/09345 ,  H05K2201/10689 ,  H05K2203/162

Abstract: Noise frequency generated from a circuit is determined. The distance between two arbitrary lines of a plurality of power feed lines or a plurality of power return lines extending parallel to each other is determined on the basis of the determined noise frequency in question. The distance between jumper lines for bridging the two arbitrary lines is determined on the basis of the noise frequency, thereby suppressing emitted noise which can be generated on a printed circuit board.

Abstract translation: 确定从电路产生的噪声频率。 基于所确定的噪声频率来确定多个馈电线的两条任意线之间的距离或者彼此平行延伸的多条功率返回线之间的距离。 基于噪声频率确定用于桥接两条任意行的跨接线之间的距离，从而抑制可能在印刷电路板上产生的发射噪声。

公开(公告)号：US6157251A

公开(公告)日：2000-12-05

申请号：US439918

申请日：1999-11-12

Applicant: Sergio D. Camerlo

Inventor： Sergio D. Camerlo

IPC: G06F1/10 ,  H05K1/02 ,  H01L25/00

CPC classification number: H05K1/0233 ,  G06F1/10 ,  H05K1/0231 ,  H05K1/0215 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

公开(公告)号：US5095407A

公开(公告)日：1992-03-10

申请号：US397352

申请日：1989-08-23

Applicant: Yukio Kanezawa ,  Masayuki Watanabe ,  Toshio Sugano

Inventor： Yukio Kanezawa ,  Masayuki Watanabe ,  Toshio Sugano

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/28 ,  H05K3/42

CPC classification number: H05K1/0224 ,  H05K1/0216 ,  H05K1/0271 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H05K1/0253 ,  H05K1/0289 ,  H05K1/141 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/09681 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K3/28 ,  H05K3/427

Abstract: A face-mounting type memory module board wherein the number of through-holes is reduced by a large margin in order to improve the reliability of the board. V.sub.CC and V.sub.SS plates which have heretofore been provided inside a multi-layer wiring board are disposed on the reverse surface of a single-layer wiring board, and other wirings are disposed on its obverse surface by making use of a fine process, thereby greatly reducing the number of through-holes required.

Abstract translation: 为了提高电路板的可靠性，面安装型存储模块板的通孔减少了很多。 迄今为止在多层布线基板内设置的VCC和VSS板设置在单层布线板的背面上，并且通过利用精细工艺将其它布线布置在其正面上，从而大大降低 所需的通孔数量。

公开(公告)号：US4250616A

公开(公告)日：1981-02-17

申请号：US23146

申请日：1979-03-23

Applicant: John J. Klimek ,  Charles L. Tesch ,  Ernest M. Feo ,  Ronald W. Lesky

Inventor： John J. Klimek ,  Charles L. Tesch ,  Ernest M. Feo ,  Ronald W. Lesky

IPC: H01R12/04 ,  B32B15/08 ,  H01R12/18 ,  H05K1/02 ,  H05K1/05 ,  H05K3/00 ,  H05K3/40 ,  H05K3/44 ,  H05K3/46 ,  H05K7/08 ,  H05K3/36

CPC classification number: H05K1/0265 ,  H05K3/445 ,  H05K3/4641 ,  H05K7/08 ,  H05K1/0262 ,  H05K2201/0352 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10189 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K3/0052 ,  H05K3/4046 ,  Y10T156/108 ,  Y10T29/49126

Abstract: A method of forming an electrical backplane comprising providing an initially oversized ground and potential plate, forming discontinuous slots in a staggered relationship near the edges of the top surface of one of the plates and the bottom surface of the other plates, laminating the plates together by filling the slots with insulative material and trimming the edge portions off by cutting through the filled slots and webs connecting the slots whereby exposed backplane edges lie opposite insulation in the slots of the plates.

Abstract translation: 一种形成电背板的方法，包括提供初始尺寸过大的接地和电位板，在其中一个板的顶表面和另一个板的底表面的边缘附近以交错关系形成不连续的槽，通过 用绝缘材料填充槽并通过切穿连接槽的填充槽和腹板来剪切边缘部分，从而暴露的背板边缘与板的槽中的绝缘相对。

公开(公告)号：US20240074034A1

公开(公告)日：2024-02-29

申请号：US18261250

申请日：2021-11-29

Applicant: HITACHI ASTEMO, LTD.

Inventor： Akira ISHII ,  Tomio SAKASHITA

IPC: H05K1/02 ,  H05K1/14

CPC classification number: H05K1/0218 ,  H05K1/14 ,  H05K2201/09345

Abstract: An electronic control device includes a plurality of circuit boards that transmit signals to each other and a power supply connector for direct-current power. A ground line connected to a ground terminal of the power supply connector is connected to a ground of one of the plurality of circuit boards by way of a ground of another one of the plurality of circuit boards. In this way, the electronic control device including the plurality of circuit boards needs fewer noise reduction components while enabling easier routing of ground lines.

公开(公告)号：US20170132436A1

公开(公告)日：2017-05-11

申请号：US15304232

申请日：2015-04-09

Applicant: NIDEC SANKYO CORPORATION

Inventor： Kazuhiro GOMI ,  Ikuro KURIBAYASHI

IPC: G06F21/86 ,  G06K7/10 ,  G06K7/08

CPC classification number: G06F21/86 ,  G06K7/00 ,  G06K7/087 ,  G06K7/10009 ,  H05K1/0219 ,  H05K1/0275 ,  H05K2201/09345

Abstract: Provided is a printed circuit board having a breakdown detection pattern formed thereon for preventing illicit acquisition of sensitive data, the printed circuit board being configured so that false detection of a disconnection or a short in the breakdown detection pattern can be prevented. The printed circuit board (7) comprises a breakdown detection pattern layer (32) wherein a breakdown detection pattern is formed for detecting a disconnection and/or a shorting thereof, a first pattern layer (31) disposed more to a Y1 direction side than the breakdown detection pattern layer (32), a second pattern layer (33) disposed more to a Y2 direction side than the breakdown detection pattern layer (32), and signal pattern layers (34 to 36) disposed more to the Y2 direction side than the second pattern layer (33). Formed in the first pattern layer (31) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y1 direction side. Formed in the second pattern layer (33) are a grounding pattern and a power source pattern covering the breakdown detection pattern from the Y2 direction side.

公开(公告)号：US20170118842A1

公开(公告)日：2017-04-27

申请号：US14918678

申请日：2015-10-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce J. CHAMBERLIN ,  Andreas HUBER ,  Harald HUELS ,  Thomas STRACH ,  Thomas-Michael WINKEL

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/09 ,  H05K1/02 ,  H05K3/40 ,  H05K3/00 ,  H05K1/11

CPC classification number: H05K1/184 ,  B23K1/0016 ,  H05K1/0298 ,  H05K1/092 ,  H05K1/111 ,  H05K1/113 ,  H05K1/116 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K1/185 ,  H05K1/186 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/429 ,  H05K3/46 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09327 ,  H05K2201/09345 ,  H05K2201/09381 ,  H05K2201/09518 ,  H05K2201/09545 ,  H05K2201/096 ,  H05K2201/09845 ,  H05K2201/10 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10174

Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.

公开(公告)号：US09609742B2

公开(公告)日：2017-03-28

申请号：US14014652

申请日：2013-08-30

Applicant: SK hynix Inc.

Inventor： Eul Chul Jang ,  Qwan Ho Chung ,  Sang Joon Lim ,  Sung Woo Han

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H05K1/02 ,  H01L23/498 ,  H01L23/552

CPC classification number: H05K1/0224 ,  H01L23/49838 ,  H01L23/552 ,  H01L2924/0002 ,  H05K1/0219 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09681 ,  H05K2201/097 ,  H05K2201/09727 ,  H01L2924/00

Abstract: Package substrates are provided. The package substrate may include a power line and a ground line on a first surface of a substrate body; a plurality of signal lines on the first surface between the power line and the ground line; and a lower ground pattern and a lower power pattern positioned on a second surface of the substrate body opposite to the first surface. The lower ground pattern may be disposed to be opposite to the power line and the lower power pattern may be disposed to be opposite to the ground line. Related semiconductor packages are also provided.