公开(公告)号：US20150049447A1

公开(公告)日：2015-02-19

申请号：US14460587

申请日：2014-08-15

Applicant: Point Engineering Co., Ltd.

Inventor： Bum Mo Ahn ,  Seung Ho Park ,  Kyoung Ja Yun

IPC: H05K3/00 ,  H05K3/46 ,  H05K1/18

CPC classification number: H05K3/0052 ,  H01L33/48 ,  H01L33/62 ,  H01L2924/0002 ,  H05K1/183 ,  H05K2201/09718 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/10 ,  H05K2201/10106 ,  H05K2201/10121 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A base substrate which prevents burrs generated during the cutting process includes: multiple conductive layers stacked in one direction with respect to the base substrate; at least one insulation layer being alternately stacked with said conductive layers and electrically separating said conductive layers; and a through-hole penetrating said base substrate covering said insulation layer at the contact region where said cut surface and said insulation layer meet during the cutting of said base substrate in accordance with a predetermined region of the chip substrate. A method of manufacturing the base substrate includes alternately stacking conductive layers and insulation layers and forming a through-hole.

Abstract translation: 防止在切割过程中产生的毛刺的基底基板包括：相对于基底基板沿一个方向堆叠的多个导电层; 至少一个绝缘层与所述导电层交替堆叠并电分离所述导电层; 以及根据所述芯片基板的预定区域，在切割所述基底基板期间，在所述切割面和所述绝缘层相接触的接触区域处覆盖所述绝缘层的通孔。 制造基底基板的方法包括交替地堆叠导电层和绝缘层并形成通孔。

公开(公告)号：US20140374148A1

公开(公告)日：2014-12-25

申请号：US14138383

申请日：2013-12-23

Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.

Inventor： KUO-FU SU ,  GWUN-JIN LIN

IPC: H05K1/11

CPC classification number: H05K3/4061 ,  H05K1/0283 ,  H05K1/115 ,  H05K1/118 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/1572

Abstract: A conductive connection structure for a conductive wiring layer of a flexible circuit board includes a first through hole and a second through hole formed in a lamination structure including a conductive wiring layer, a first covering layer, and a second covering layer. The first through hole extends through the first covering layer and the conductive wiring layer. The second through hole extends through the second covering layer. The second through hole is formed at a location corresponding to an exposed zone on a second surface of the conductive wiring layer and communicates with the first through hole. A first conductive paste layer is formed on a surface of the first covering layer and fills in the first through hole to form a pillar portion in the first through hole. The pillar portion has a bottom end forming a curved cap. The exposed zone of the second surface of the conductive wiring layer is at least partially covered by the curved cap.

Abstract translation: 用于柔性电路板的导电布线层的导电连接结构包括形成在包括导电布线层，第一覆盖层和第二覆盖层的叠层结构中的第一通孔和第二通孔。 第一通孔延伸穿过第一覆盖层和导电布线层。 第二通孔延伸穿过第二覆盖层。 第二通孔形成在与导电布线层的第二表面上的暴露区相对应的位置处，并与第一通孔连通。 第一导电浆料层形成在第一覆盖层的表面上并填充在第一通孔中，以在第一通孔中形成柱部分。 柱部具有形成弯曲帽的底端。 导电布线层的第二表面的暴露区域至少部分被弯曲的盖子覆盖。

公开(公告)号：US20140362542A1

公开(公告)日：2014-12-11

申请号：US14202333

申请日：2014-03-10

Applicant: BOE Technology Group Co., LTD. ,  Hefei BOE Optoelectronics Technology Co., LTD.

Inventor： Juncai Ma

IPC: H05K1/02

CPC classification number: H05K1/111 ,  G02F1/13452 ,  G02F1/13454 ,  G02F1/13458 ,  H05K1/181 ,  H05K2201/094 ,  H05K2201/09436 ,  H05K2201/09709 ,  H05K2201/09736 ,  H05K2201/09845 ,  H05K2201/10234 ,  Y02P70/611

Abstract: The present invention relates to an array substrate assembly and a display device. The array substrate assembly comprises a substrate; a first metal line formed at one side of the substrate; an insulating layer formed on the first metal line; a second metal line formed on the insulating layer, wherein one end of the second metal line connected with a driving circuit is formed with a second terminal, wherein in a thickness direction of the substrate, a distance between a surface of the second terminal away from the one side of the substrate and the substrate is less than a distance between a surface of the second metal line away from the one side of the substrate and the substrate. The display device includes the array substrate assembly. With the solution of the present invention, when the array substrate assembly is connected to IC or COF, deformation difference between a conducting gold ball at a gate line terminal and a conducting gold ball at a date line is small, thus impedances at the two terminals are close to each other, and therefore image quality of the display device is improved.

Abstract translation: 本发明涉及阵列基板组件和显示装置。 阵列基板组件包括基板; 形成在所述基板一侧的第一金属线; 形成在所述第一金属线上的绝缘层; 形成在绝缘层上的第二金属线，其中与驱动电路连接的第二金属线的一端形成有第二端子，其中在基板的厚度方向上，第二端子的表面之间的距离远离 基板和基板的一侧小于离开基板的一侧的第二金属线的表面与基板之间的距离。 显示装置包括阵列基板组件。 利用本发明的解决方案，当阵列基板组件连接到IC或COF时，栅极线端子处的导电金球与日期线处的导电金球之间的变形差小，因此两个端子处的阻抗 彼此接近，因此改善了显示装置的图像质量。

公开(公告)号：US20140304977A1

公开(公告)日：2014-10-16

申请号：US14356209

申请日：2012-08-31

Applicant: SHENZHEN SUNTAK MULTILAYER PCB CO., LTD.

Inventor： Jianyuan Song ,  Weihong Peng ,  Pingping Xie ,  Dong Liu

IPC: H05K3/00

CPC classification number: H05K3/00 ,  H05K1/0269 ,  H05K3/0017 ,  H05K3/0044 ,  H05K3/0047 ,  H05K3/0073 ,  H05K3/12 ,  H05K3/188 ,  H05K3/3452 ,  H05K3/42 ,  H05K3/425 ,  H05K3/428 ,  H05K3/4623 ,  H05K3/4629 ,  H05K2201/09036 ,  H05K2201/09845 ,  H05K2203/0315 ,  H05K2203/162 ,  Y10T29/49004 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49179

Abstract: A fabrication process of a stepped circuit board, comprises the following steps of: A) cutting a circuit board substrate, printing patterns on an inner layer thereof, performing etching, stepped groove grinding, washer milling, brownification and lamination processing on the inner layer, and then drilling holes on an outer layer thereof; B) depositing copper on the outer layer of the circuit board substrate with drilled holes, and then electroplating the entire circuit board substrate; C) performing pattern transfer; D) performing pattern copper plating on the circuit board substrate, and grinding the shape of a connecting piece (SET) on the circuit board substrate, and then etching the outer layer; E) printing a solder mask and texts in a silk-screen manner; F) depositing nickel immersion gold on the entire substrate, then printing characters in a silk-screen manner; and G) testing and inspecting the electrical performance and appearance of a finished board.

Abstract translation: 步进电路板的制造工艺包括以下步骤：A）切割电路板基板，在其内层上印刷图案，对内层进行蚀刻，阶梯槽研磨，垫片研磨，褐化和层压处理， 然后在其外层上钻孔; B）在钻孔的电路板基板的外层上沉积铜，然后电镀整个电路板基板; C）执行模式转移; D）在电路板基板上进行图案镀铜，并研磨电路板基板上的连接件（SET）的形状，然后蚀刻外层; E）以丝网印刷方式印刷焊接面罩和文字; F）在整个基板上沉积镍浸金，然后以丝网印刷方式印刷字符; 和G）测试和检查成品板的电气性能和外观。

公开(公告)号：US20140110159A1

公开(公告)日：2014-04-24

申请号：US13960897

申请日：2013-08-07

Applicant: Chien-Cheng Wei ,  Wu-Hui Cheng

Inventor： Chien-Cheng Wei ,  Wu-Hui Cheng

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/00

CPC classification number: H05K1/0271 ,  H05K1/0265 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/108 ,  H05K3/146 ,  H05K3/16 ,  H05K3/388 ,  H05K2201/0338 ,  H05K2201/09845 ,  H05K2203/058 ,  H05K2203/1476 ,  H05K2203/1572

Abstract: A stress-reduced circuit board includes an insulating substrate, and first and second electrically conductive layers which are stacked one upon the other, and which respectively have peripheral marginal regions that are configured in a stepped arrangement. The first electrically conductive layer is configured to have an area dimension larger than that of the second electrically conductive layer and a thickness not greater than that of the second electrically conductive layer so as to minimize stress caused by a difference in coefficients of thermal expansion between the insulating substrate and the first and second electrically conductive layers.

Abstract translation: 应力降低电路板包括绝缘基板以及彼此堆叠的第一和第二导电层，并且分别具有以阶梯式布置的周边边缘区域。 第一导电层被配置为具有比第二导电层的面积尺寸更大的面积尺寸，并且其厚度不大于第二导电层的厚度，以便使由于第二导电层之间的热膨胀系数的差异而引起的应力最小化 绝缘基板和第一和第二导电层。

公开(公告)号：US08705238B2

公开(公告)日：2014-04-22

申请号：US12926710

申请日：2010-12-06

Applicant: Yasutaka Nakashiba ,  Kenta Ogawa

Inventor： Yasutaka Nakashiba ,  Kenta Ogawa

IPC: H05K7/20 ,  H01L23/48 ,  H01F7/06

CPC classification number: H01L28/10 ,  G11C5/005 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49855 ,  H01L23/5227 ,  H01L23/562 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L27/0688 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/15183 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K1/117 ,  H05K3/0052 ,  H05K3/284 ,  H05K2201/0949 ,  H05K2201/09845 ,  H05K2203/0228 ,  H05K2203/1316 ,  H05K2203/1572 ,  Y10T29/4902 ,  Y10T29/4913 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A storage element is provided in a semiconductor chip, and an inductor and a driver circuit are provided in another semiconductor chip. An external terminal is a contact type terminal, and at least some external terminals are a power supply terminal and a ground terminal. A sealing resin layer is formed over a first surface of an interconnect substrate and seals the semiconductor chips but does not cover the external terminal. The inductor is formed at a surface of the semiconductor chip not facing the interconnect substrate.

Abstract translation: 存储元件设置在半导体芯片中，并且电感器和驱动电路设置在另一半导体芯片中。 外部端子是接触型端子，至少一些外部端子是电源端子和接地端子。 在互连基板的第一表面上形成密封树脂层，并密封半导体芯片，但不覆盖外部端子。 电感器形成在不面向互连基板的半导体芯片的表面。

公开(公告)号：US20140090877A1

公开(公告)日：2014-04-03

申请号：US14041743

申请日：2013-09-30

Applicant: IBIDEN CO., LTD.

Inventor： Fumitaka TAKAGI ,  Nobuhisa Kuroda ,  Mariko Kimura

IPC: H05K1/18 ,  H05K3/02

CPC classification number: H05K1/183 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83385 ,  H01L2224/83411 ,  H01L2224/83444 ,  H01L2224/83455 ,  H01L2224/83464 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/181 ,  H05K3/02 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/09845 ,  H05K2201/10515 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed wiring board includes an interlayer resin insulation layer, a pad structure formed on the interlayer resin insulation layer and positioned to mount a semiconductor device, and a solder-resist layer formed on the interlayer resin insulation layer and having an opening portion exposing a portion of the pad structure from the solder-resist layer. The opening portion of the solder-resist layer has a bottom surface such that the bottom surface of the opening portion is exposing an upper surface and a portion of a side surface of the pad structure.

Abstract translation: 印刷布线板包括层间树脂绝缘层，形成在层间树脂绝缘层上并定位成安装半导体器件的焊盘结构，以及形成在层间树脂绝缘层上的阻焊层，并且具有露出部分 的焊料结构。 阻焊层的开口部分具有底表面，使得开口部分的底表面暴露焊盘结构的上表面和侧表面的一部分。

公开(公告)号：US20140036461A1

公开(公告)日：2014-02-06

申请号：US13883386

申请日：2011-10-27

Applicant: Ravi Palaniswamy ,  Arokiaraj Jesudoss ,  Alejandro Aldrin II Agcaoili Narag ,  James R White ,  Fong Liang Tan ,  Andrew J Ouderkirk ,  Justine A Mooney ,  Nathan P Kreutter ,  Qihong Nie ,  Jian Xia Gao

Inventor： Ravi Palaniswamy ,  Arokiaraj Jesudoss ,  Alejandro Aldrin II Agcaoili Narag ,  James R White ,  Fong Liang Tan ,  Andrew J Ouderkirk ,  Justine A Mooney ,  Nathan P Kreutter ,  Qihong Nie ,  Jian Xia Gao

IPC: H05K1/02

CPC classification number: H05K1/0206 ,  H01L24/32 ,  H01L33/486 ,  H01L33/64 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/12032 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/15747 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/021 ,  H05K1/189 ,  H05K2201/09827 ,  H05K2201/09845 ,  H05K2201/10106 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Provided is a flexible light emitting semiconductor device (26), such as an LED device, that includes a flexible dielectric layer (12) having first and second major surfaces and at least one via (10) extending through the dielectric layer from the first to the second major surface, with a conductive layer (19, 20, 18) on each of the first and second major surfaces and in the via. The conductive layer (18) in the via supports a light emitting semiconductor device (26) and is electrically isolated from the conductive layer (19) on the first major surface of the dielectric layer.

Abstract translation: 提供了一种诸如LED器件的柔性发光半导体器件（26），其包括具有第一和第二主表面的柔性介电层（12）和至少一个通孔（10），该通孔（10）从第一至第 所述第二主表面在所述第一和第二主表面中的每个表面上以及所述通孔中具有导电层（19,20,18）。 通孔中的导电层（18）支撑发光半导体器件（26），并且与电介质层的第一主表面上的导电层（19）电隔离。

公开(公告)号：US20140000940A1

公开(公告)日：2014-01-02

申请号：US13880589

申请日：2011-10-27

Applicant: Yurie Onitsuka ,  Yousuke Moriyama

Inventor： Yurie Onitsuka ,  Yousuke Moriyama

IPC: H05K1/18

CPC classification number: H05K1/18 ,  H01L23/13 ,  H01L23/36 ,  H01L23/49805 ,  H01L33/486 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/02 ,  H05K3/0052 ,  H05K3/0061 ,  H05K2201/0769 ,  H05K2201/09145 ,  H05K2201/0919 ,  H05K2201/09845 ,  H01L2924/00011 ,  H01L2924/00

Abstract: A wiring board includes an insulating substrate having a side surface including a protrusion portion or a recess portion and a lower surface having a metal member bonded thereto; a wiring conductor embedded in the insulating substrate and having an exposed portion partially exposed above the protrusion portion or the recess portion from the side surface of the insulating substrate; and a metal member bonded to the lower surface of the insulating substrate. It is possible to suppress occurrence of ion migration between the wiring conductor and the metal member by increasing a distance between the exposed portion and the metal member without increasing a thickness of the wiring board.

Abstract translation: 布线基板包括绝缘基板，该绝缘基板具有包括突出部或凹部的侧表面和与其接合的金属部件的下表面; 嵌入绝缘基板中的布线导体，并且具有从绝缘基板的侧面突出部分或凹部的部分露出的暴露部分; 以及结合到绝缘基板的下表面的金属构件。 通过在不增加布线板的厚度的情况下增加露出部与金属构件的距离，能够抑制布线导体与金属构件之间的离子迁移的发生。

公开(公告)号：US20130316551A1

公开(公告)日：2013-11-28

申请号：US13481176

申请日：2012-05-25

Applicant: James A. Day, JR. ,  Zachary B. Durham ,  Luke D. Remis ,  Tony C. Sass ,  Gregory D. Sellman

Inventor： James A. Day, JR. ,  Zachary B. Durham ,  Luke D. Remis ,  Tony C. Sass ,  Gregory D. Sellman

IPC: H01R12/58 ,  H05K3/30

CPC classification number: H05K13/04 ,  H01R12/585 ,  H05K1/115 ,  H05K3/308 ,  H05K3/325 ,  H05K2201/09845 ,  H05K2201/1059 ,  H05K2201/10856 ,  H05K2201/10878

Abstract: A universal press-fit connection allows a component having a connector pin to be connected to a compatible plated through hole of a circuit board regardless of circuit board thickness. The connector pin includes a proximate end adjacent the component, a distal end with a fork lock, and a compliant portion between the proximate and distal ends. A multi-width through hole includes a first portion partially extending through the circuit board and a second, wider portion extending beyond the first portion. The fork lock initially moves radially inward upon insertion into the first portion via flexing of the compliant portion, and re-expands when entering the second portion. The compliant portion engages the through hole and the fork lock secures the connector pin in the through hole.

Abstract translation: 通用压配合连接允许具有连接器引脚的部件连接到电路板的兼容的电镀通孔，而与电路板厚度无关。 连接器销包括邻近部件的近端，具有叉锁的远端以及近端和远端之间的柔顺部分。 多宽度通孔包括部分延伸穿过电路板的第一部分和延伸超过第一部分的第二较宽部分。 当通过柔性部分的弯曲插入到第一部分中时，叉锁首先向内径向移动，并且当进入第二部分时，叉锁重新膨胀。 柔性部分接合通孔，叉锁将连接器销固定在通孔中。