公开(公告)号：US09153640B2

公开(公告)日：2015-10-06

申请号：US14320633

申请日：2014-06-30

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chun-I Hsieh ,  Daniel Damjanovic

IPC: H01L21/20 ,  H01L49/02 ,  H01G4/10 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01G4/10 ,  H01L21/02186 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/0234

Abstract: A process of forming a capacitor structure includes providing a substrate. Next, a first electrode is deposited onto the substrate. Later, a water-based ALD process is performed to deposit a transitional amorphous TiO2 layer on the first electrode. Subsequently, the transitional amorphous TiO2 layer is treated by oxygen plasma to transform the entire transitional amorphous TiO2 layer into a rutile TiO2 layer. Finally, a second electrode is deposited on the rutile TiO2 layer.

Abstract translation: 形成电容器结构的工艺包括提供衬底。 接下来，将第一电极沉积到基板上。 然后，进行水性ALD工艺以在第一电极上沉积过渡的无定形TiO 2层。 随后，通过氧等离子体处理过渡非晶态TiO 2层，将整个非晶态TiO 2层转化为金红石型TiO 2层。 最后，第二电极沉积在金红石TiO 2层上。

公开(公告)号：US09070871B2

公开(公告)日：2015-06-30

申请号：US14529176

申请日：2014-10-31

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chun-I Hsieh ,  Chang-Rong Wu

IPC: H01L21/00 ,  H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  H01F10/32 ,  H01F41/30 ,  H01L43/08 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/308 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.

Abstract translation: 磁阻随机存取存储器（MRAM）元件包括嵌入第一绝缘层中的底电极; 在所述第一绝缘层上的第二绝缘层的第一通孔中的环形参考层，所述环形参考层位于所述底部电极的上方; 填充第一通孔的第一间隙填充材料层; 覆盖所述环形基准层，所述第二绝缘层和所述第一间隙填充材料层的阻挡层; 在所述第二绝缘层上的第三绝缘层的第二通孔中的环形自由层，所述环形自由层位于所述环形参考层的上方; 以及堆叠在环形自由层上的顶部电极。

公开(公告)号：US20150064893A1

公开(公告)日：2015-03-05

申请号：US14534192

申请日：2014-11-06

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chin-Te Kuo ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/3083 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

Abstract: A method for forming a trench MOS structure. First, a substrate, an epitaxial layer, a doping region and a doping well are provided. The substrate has a first conductivity type, a first side and a second side opposite to the first side. The epitaxial layer has the first conductivity type and is disposed on the first side. The doping well has a second conductivity type and is disposed on the epitaxial layer. The doping region has the first conductivity type and is disposed on the doping well. A gate trench penetrates the doping region and the doping well. The doping well is partially removed to form a bottom section of the gate trench. A gate isolation is formed to cover the inner wall of the bottom section and a top section of the gate trench. The gate trench is filled with a conductive material to form a trench gate.

Abstract translation: 一种形成沟槽MOS结构的方法。 首先，提供衬底，外延层，掺杂区和掺杂阱。 衬底具有第一导电类型，第一侧和与第一侧相对的第二侧。 外延层具有第一导电类型并且设置在第一侧。 掺杂阱具有第二导电类型并且设置在外延层上。 掺杂区域具有第一导电类型并且被布置在掺杂阱上。 栅极沟槽穿透掺杂区域和掺杂阱。 部分去除掺杂阱以形成栅极沟槽的底部。 形成栅极隔离以覆盖底部的内壁和栅极沟槽的顶部。 栅极沟槽填充有导电材料以形成沟槽栅极。

公开(公告)号：US08871103B2

公开(公告)日：2014-10-28

申请号：US14049232

申请日：2013-10-09

Applicant: Nanya Technology Corp.

Inventor： Brett Busch ,  Gowri Damarla ,  Anurag Jindal ,  Chia-Yen Ho ,  Thy Tran

IPC: H01L21/306 ,  H01L21/321 ,  H01L27/108

CPC classification number: H01L21/30625 ,  H01L21/3212 ,  H01L27/10894

Abstract: A blanket stop layer is conformally formed on a layer with a large step height. A first chemical mechanical polishing process is performed to remove the blanket stop layer atop the layer in the raised region. A second chemical mechanical polishing process is performed to planarize the wafer using the blanket stop layer as a stop layer when the layer is lower than or at a same level as the blanket stop layer or using the layer as a stop layer when the blanket stop layer is lower than or at a same level as the layer, or a selective dry etch is performed to remove the layer in the raised region. Thus, the layer in the raised region can be easily removed without occurrence of dishing in the non-raised region which is protected by the blanket stop layer.

公开(公告)号：US20140315368A1

公开(公告)日：2014-10-23

申请号：US14320633

申请日：2014-06-30

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chun-I Hsieh ,  Daniel Damjanovic

IPC: H01L49/02 ,  H01L21/02

CPC classification number: H01L28/40 ,  H01G4/10 ,  H01L21/02186 ,  H01L21/02271 ,  H01L21/02323 ,  H01L21/0234

Abstract: A process of forming a capacitor structure includes providing a substrate. Next, a first electrode is deposited onto the substrate. Later, a water-based ALD process is performed to deposit a transitional amorphous TiO2 layer on the first electrode. Subsequently, the transitional amorphous TiO2 layer is treated by oxygen plasma to transform the entire transitional amorphous TiO2 layer into a rutile TiO2 layer. Finally, a second electrode is deposited on the rutile TiO2 layer.

Abstract translation: 形成电容器结构的工艺包括提供衬底。 接下来，将第一电极沉积到基板上。 然后，进行水性ALD工艺以在第一电极上沉积过渡的无定形TiO 2层。 随后，通过氧等离子体处理过渡非晶态TiO 2层，将整个非晶态TiO 2层转化为金红石型TiO 2层。 最后，第二电极沉积在金红石TiO 2层上。

公开(公告)号：US20140272674A1

公开(公告)日：2014-09-18

申请号：US13801945

申请日：2013-03-13

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Yu-Mei Ni ,  Chun-Yen Huang ,  Pei-Cheng Fan

IPC: G03F1/22

CPC classification number: G03F1/22 ,  G03F1/24

Abstract: A mask structure, including a substrate; an absorber layer formed on the substrate; and a patterned reflection layer formed on the absorber layer. Optionally, the mask structure may further include a buffer layer, a conductive coating, or combinations thereof. The buffer layer may be formed between the absorber layer and the reflection layer, and the conductive coating may be formed at a back side of the substrate.

Abstract translation: 一种掩模结构，包括基底; 形成在所述基板上的吸收体层; 以及形成在吸收体层上的图案化反射层。 任选地，掩模结构还可以包括缓冲层，导电涂层或其组合。 缓冲层可以形成在吸收层和反射层之间，并且导电涂层可以形成在衬底的背面。

公开(公告)号：US20140264640A1

公开(公告)日：2014-09-18

申请号：US13846169

申请日：2013-03-18

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Shin-Yu Nieh ,  Tieh-Chiang Wu ,  Wei-Ming Liao ,  Jei-Cheng Huang ,  Hai-Han Hung ,  Hsiu-Chun Lee

IPC: H01L29/49 ,  H01L29/78

CPC classification number: H01L29/4966 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28105 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66553

Abstract: The invention provides a semiconductor device, including: a substrate; a U-shaped gate dielectric layer formed on the substrate; and a dual work function metal gate layer on the inner surface of U-shaped gate dielectric layer, wherein the dual work function metal gate layer includes a first conductive type metal layer and a second conductive type metal layer.

Abstract translation: 本发明提供一种半导体器件，包括：衬底; 形成在所述基板上的U形栅介质层; 以及在U形栅极电介质层的内表面上的双功函数金属栅极层，其中双功函数金属栅极层包括第一导电型金属层和第二导电型金属层。

公开(公告)号：US20140252545A1

公开(公告)日：2014-09-11

申请号：US13786463

申请日：2013-03-06

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chien-An Yu ,  Chih-Huang Wu

IPC: H01L27/04

CPC classification number: H01L27/04 ,  H01L23/5223 ,  H01L27/0629 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10894 ,  H01L28/40 ,  H01L28/60 ,  H01L28/91 ,  H01L2924/0002 ,  Y10S257/906 ,  H01L2924/00

Abstract: A semiconductor memory device includes a substrate having thereon a memory array region and a periphery circuit region. A first dielectric layer covers the memory array region and the periphery circuit region on the substrate. A second dielectric layer covers the memory array region and the periphery circuit region on the first dielectric layer. At least a capacitor structure is provided in the memory array region. The capacitor structure includes an electrode material layer embedded in the second dielectric layer. The semiconductor memory device further includes a contact structure comprising the electrode material layer.

Abstract translation: 半导体存储器件包括其上具有存储器阵列区域和外围电路区域的衬底。 第一电介质层覆盖衬底上的存储器阵列区域和外围电路区域。 第二电介质层覆盖第一电介质层上的存储器阵列区域和外围电路区域。 在存储器阵列区域中至少提供一个电容器结构。 电容器结构包括嵌入在第二电介质层中的电极材料层。 半导体存储器件还包括包括电极材料层的接触结构。

公开(公告)号：US08698235B2

公开(公告)日：2014-04-15

申请号：US13958620

申请日：2013-08-05

Applicant: Nanya Technology Corp.

Inventor： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/4236 ,  H01L21/28114 ,  H01L21/76224 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66553

Abstract: A slit recess channel gate is provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer.

Abstract translation: 提供狭缝凹槽通道门。 狭缝凹槽通道门包括衬底，栅介质层，第一导电层和第二导电层。 衬底具有第一沟槽。 栅介质层设置在第一沟槽的表面上，第一导电层嵌入第一沟槽中。 第二导电层设置在第一导电层上并与主表面上的第一导电层对准，其中第二导电层的底表面积基本上小于第二导电层的顶表面积。

公开(公告)号：US20130252348A1

公开(公告)日：2013-09-26

申请号：US13902877

申请日：2013-05-27

Applicant: NANYA TECHNOLOGY CORP.

Inventor： Chun-I Hsieh ,  Chang-Rong Wu

IPC: H01L43/12

CPC classification number: H01L43/12 ,  B82Y25/00 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/308 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive random access memory (MRAM) element includes a bottom electrode embedded in a first insulating layer; an annular reference layer in a first via hole of a second insulating layer on the first insulating layer, the annular reference layer being situated above the bottom electrode; a first gap fill material layer filling the first via hole; a barrier layer covering the annular reference layer, the second insulating layer and the first gap fill material layer; an annular free layer in a second via hole of a third insulating layer on the second insulating layer, the annular free layer being situated above the annular reference layer; and a top electrode stacked on the annular free layer.

Abstract translation: 磁阻随机存取存储器（MRAM）元件包括嵌入第一绝缘层中的底电极; 在所述第一绝缘层上的第二绝缘层的第一通孔中的环形参考层，所述环形参考层位于所述底部电极的上方; 填充第一通孔的第一间隙填充材料层; 覆盖所述环形基准层，所述第二绝缘层和所述第一间隙填充材料层的阻挡层; 在所述第二绝缘层上的第三绝缘层的第二通孔中的环形自由层，所述环形自由层位于所述环形参考层的上方; 以及堆叠在环形自由层上的顶部电极。