公开(公告)号：US5142239A

公开(公告)日：1992-08-25

申请号：US702490

申请日：1991-05-20

Applicant: Daniel C. Brayton ,  Ngai-Ming Lau

Inventor： Daniel C. Brayton ,  Ngai-Ming Lau

IPC: H03F1/22 ,  H03F1/42 ,  H03F3/191 ,  H03F3/60 ,  H05K1/02 ,  H05K1/03 ,  H05K1/14 ,  H05K1/16 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36

CPC classification number: H03F3/191 ,  H05K1/141 ,  H05K1/0216 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/167 ,  H05K2201/0792 ,  H05K2201/10166 ,  H05K2203/049 ,  H05K3/328 ,  H05K3/341 ,  H05K3/368

Abstract: A wide bandwidth linear amplifier (10) that has an operating band in excess of 1 GHz mounts the high power dissipating components (11) of the amplifier (10), and the components 917, 18) that control the high frequency gain and stability of the amplifier (10) onto a daughter board (32) that has a high thermal conductivity. The daughter board (32) and the remaining circuit components (21, 22, 23, 24, 26a, 26b) are then mounted on a mother board (31) that has a lower thermal conductivity. The assembly (30) reduces the circuit's parasitic inductance (46, 47, 48, 49) and parasitic capacitance (51, 52), and provides unconditional stability at high frequencies.

Abstract translation: 具有超过1GHz的工作频带的宽带宽线性放大器（10）安装放大器（10）的高功率耗散部件（11）和控制高频增益和稳定性的部件917,18） 放大器（10）到具有高导热性的子板（32）上。 然后将子板（32）和剩余的电路部件（21,22,23,24,26a，26b）安装在具有较低热导率的母板（31）上。 组件（30）减小了电路的寄生电感（46,47,48,49）和寄生电容（51,52），并在高频下提供了无条件的稳定性。

公开(公告)号：US5093640A

公开(公告)日：1992-03-03

申请号：US414832

申请日：1989-09-29

Applicant: Richard S. Bischof

Inventor： Richard S. Bischof

IPC: H01P1/04 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/36

CPC classification number: H05K1/0243 ,  H01P1/047 ,  H05K1/111 ,  H05K1/117 ,  H05K1/142 ,  H05K2201/0792 ,  H05K2201/09072 ,  H05K2201/09727 ,  H05K2201/1028 ,  H05K2201/10636 ,  H05K3/0061 ,  H05K3/36 ,  H05K3/368 ,  Y02P70/611

Abstract: A microstrip structure includes a microstrip transmission line having a characteristic impedance, a contact pad for interconnection of the transmission line to an external device, and a compensation line connected between the contact pad and one end of the microstrip transmission line. The contact pad has larger dimensions than the transmission line and thus introduces parasitic capacitance. The compensation line is a narrow line having high impedance and is selected such that its equivalent inductance resonates with the parasitic capacitance at the upper frequency of the range of frequencies over which the transmission line is intended to be operated, thereby matching the contact pad to the transmission line.

Abstract translation: 微带结构包括具有特征阻抗的微带传输线，用于将传输线互连到外部设备的接触焊盘以及连接在接触焊盘和微带传输线的一端之间的补偿线。 接触垫具有比传输线更大的尺寸，从而引入寄生电容。 补偿线是具有高阻抗的窄线，并且被选择为使得其等效电感与在传输线旨在被操作的频率范围的较高频率处的寄生电容谐振，从而将接触焊盘与 传输线。

公开(公告)号：US5004317A

公开(公告)日：1991-04-02

申请号：US460418

申请日：1990-01-03

Applicant: Kenneth P. Jackson ,  Norman Raver

Inventor： Kenneth P. Jackson ,  Norman Raver

IPC: H01L25/00 ,  G02B6/42 ,  H01S5/00 ,  H05K1/02

CPC classification number: G02B6/4202 ,  G02B6/4249 ,  H05K1/0228 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2924/30107 ,  H05K2201/0715 ,  H05K2201/0792 ,  H05K2203/049

Abstract: In an electrical circuit including a first array and a second array of electrical components mounted on a circuit board having an electrically conductive cladding, there is provided a system for interconnecting the components of the first array to the components of the second array with parallel signal channels for reduction of crosstalk among the channels. In each of the channels, there is one electrically conductive strip formed within the cladding and providing for a path of current in a first direction, and a second conductive path for current in the reverse direction. The second path includes a wire lead formed as a partial loop extending in a plane perpendicular to a plane of the cladding, and also includes a pad formed of material of the cladding and coplanar with the conductive strip. The pad is connected to a terminus of the wire loop. The pad is insulated from the conductive strip and forms therewith a portion of a loop which generates a magnetic field in the presence of currents flowing through the two paths. Magnetic coupling provided by the wire loops has a positive coefficient of mutual inductance which cancels negative mutual inductance of loops lying in a plane of the cladding to reduce crosstalk among the channels.

公开(公告)号：US4897624A

公开(公告)日：1990-01-30

申请号：US320257

申请日：1989-02-23

Applicant: Leroy S. Wignot ,  Robert P. Parker

Inventor： Leroy S. Wignot ,  Robert P. Parker

IPC: H01G5/00 ,  H01G5/16 ,  H01G5/38 ,  H01G5/40 ,  H03J1/00 ,  H03J3/20 ,  H05K1/18

CPC classification number: H01G5/16 ,  H03J3/20 ,  H05K1/18 ,  H05K2201/0792 ,  H05K2201/1003 ,  H05K2201/10765 ,  H05K2203/171

Abstract: Apparatus for adjusting capacitance between an electronic component and external circuitry. The electronic component is unitarily provided with a plurality of conductive leads for connection to external circuitry with at least one of the leads being configured to provide integral means for adjustment of capacitance. The configured lead is bent for a turnabout of about 180 degree change of direction such that when the component is mounted on a printed circuit board the portion of the lead distal of the component extends above the board and is positionally adjustable providing adjustable capactive coupling to other circuit components.

公开(公告)号：US4477970A

公开(公告)日：1984-10-23

申请号：US364380

申请日：1982-04-01

Applicant: Robert P. Alexander ,  Robert J. Pichia ,  Stephen F. Dauksch

Inventor： Robert P. Alexander ,  Robert J. Pichia ,  Stephen F. Dauksch

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H05K3/30

CPC classification number: H05K1/184 ,  H05K1/0243 ,  H05K3/3447 ,  H05K2201/0792 ,  H05K2201/09645 ,  H05K2201/09854 ,  H05K2201/09981 ,  H05K2201/10166 ,  H05K2201/10818 ,  Y10T29/49139 ,  Y10T29/49144

Abstract: A method for preparing a printed circuit board for mounting of surface mounted RF components such that the lead inductance of the components is minimized. The process consists of producing plated through apertures in the printed circuit board to create a component body hole with lead contacts extending to the edge of the component body hole. The resulting aperture is then blanked to remove portions of the metal lining to provide electrical isolation between the lead contacts while maintaining lead contacts that extend to the edge of the component body hole. A component is then soldered into position such that solder is wicked through the plated through apertures to create solder contact of the leads at the edge of the component body hole. This results in substantial reduction in lead inductance improving RF amplifier gain and stability and improving bandwidth characteristics.

Abstract translation: 一种制备用于安装表面安装的RF部件的印刷电路板的方法，使得部件的引线电感最小化。 该方法包括在印刷电路板中生产电镀通孔，以产生具有延伸到部件主体孔的边缘的引线触头的部件主体孔。 然后将所得孔径冲切以除去金属衬里的部分，以在引线触头之间提供电隔离，同时保持延伸到部件主体孔的边缘的引线触头。 然后将组件焊接到位置，使得焊料通过镀覆的通孔被弄脏，以在部件主体孔的边缘处产生引线的焊接接触。 这导致铅电感的显着降低，从而提高RF放大器的增益和稳定性并提高带宽特性。

公开(公告)号：US20240196531A1

公开(公告)日：2024-06-13

申请号：US18586336

申请日：2024-02-23

Applicant: DexCom, Inc.

Inventor： Sean Frick ,  Louis Jung ,  David Lari

IPC: H05K1/11 ,  A61B5/00 ,  A61B5/145 ,  A61B5/1468 ,  G01N27/327 ,  H01L21/768 ,  H01L23/48 ,  H05K1/02 ,  H05K1/14 ,  H05K3/40

CPC classification number: H05K1/112 ,  A61B5/6802 ,  H01L21/768 ,  H01L23/481 ,  H05K1/0262 ,  H05K3/403 ,  A61B5/14532 ,  A61B5/14546 ,  A61B5/1468 ,  A61B5/6848 ,  G01N27/327 ,  H05K1/0219 ,  H05K1/141 ,  H05K2201/0394 ,  H05K2201/049 ,  H05K2201/0792 ,  H05K2201/09063 ,  H05K2201/09181 ,  H05K2201/10151 ,  H05K2201/10378

Abstract: An example sensor interposer employing castellated through-vias formed in a PCB includes a planar substrate defining a plurality of castellated through-vias; a first electrical contact formed on the planar substrate and electrically coupled to a first castellated through-via; a second electrical contact formed on the planar substrate and electrically coupled to a second castellated through-via, the second castellated through-via electrically isolated from the first castellated through-via; and a guard trace formed on the planar substrate, the guard trace having a first portion formed on a first surface of the planar substrate and electrically coupling a third castellated through-via to a fourth castellated through-via, the guard trace having a second portion formed on a second surface of the planar substrate and electrically coupling the third castellated through-via to the fourth castellated through-via, the guard trace formed between the first and second electrical contacts to provide electrical isolation between the first and second electrical contacts.

公开(公告)号：US20230343506A1

公开(公告)日：2023-10-26

申请号：US18216277

申请日：2023-06-29

Applicant: Rockwell Automation Technologies, Inc.

Inventor： Gennadi Sizov ,  Zoran Vrankovic ,  Gary L. Skibinski

IPC: H01F27/28 ,  H01F27/34 ,  H02M1/12 ,  H05K1/18

CPC classification number: H01F27/2804 ,  H01F27/346 ,  H01F27/2885 ,  H02M1/12 ,  H05K1/181 ,  H01F2027/2809 ,  H05K2201/08 ,  H05K2201/0792

Abstract: A system and method for integrating a magnetic component within a power converter includes a coil integrated on a PCB. The PCB includes multiple layers and traces on each layer to form a single coil or to form multiple coils on the magnetic component. The PCB further includes at least one opening in the PCB through which a core component may pass, such that the magnetic component is defined by the coils and the core material. To reduce eddy currents built up within the traces, the dimensions of traces on a layer are varied and the position of traces between layers of the PCB are varied. The widths and locations of individual traces are selected to reduce coupling of the trace to leakage fluxes within the magnetic component. A floating conductive layer may also be provided to still further reduce the magnitude of eddy currents induced within the coil.

公开(公告)号：US09819146B2

公开(公告)日：2017-11-14

申请号：US14782980

申请日：2014-04-10

Applicant: BRIGHTLOOP

Inventor： Florent Liffran ,  Olivier Rabot

IPC: H03K3/57 ,  H01S5/042 ,  H05K1/18 ,  H05K1/02

CPC classification number: H01S5/0428 ,  H03K3/57 ,  H05K1/0243 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/10015 ,  H05K2201/10174 ,  H05K2201/10446 ,  H05K2201/10545 ,  Y02P70/611

Abstract: The invention concerns a device for controlling at least one diode 2, the control device comprising an electrical card 4 comprising a printed circuit 5 on which the following are mounted: a diode 2, a front component 7 and a storage capacitor 9 connected in such a way as to form a circuit loop 17 extending substantially in a thickness of the electrical card 4.

公开(公告)号：US09113565B2

公开(公告)日：2015-08-18

申请号：US14000566

申请日：2012-06-19

Applicant: Chuanzhi Li ,  Hua Miao ,  Zhanhao Xie ,  Jun Peng

Inventor： Chuanzhi Li ,  Hua Miao ,  Zhanhao Xie ,  Jun Peng

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0243 ,  H05K1/0298 ,  H05K3/0094 ,  H05K3/4635 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09618 ,  H05K2201/09845 ,  H05K2201/10242 ,  H05K2201/10416 ,  Y10T29/49165

Abstract: A printed circuit board (PCB), a method for processing PCB and an electronic apparatus. The method for processing PCB may comprise: forming a hole in the PCB, wherein the PCB includes a metal matrix and at least two substrate layers, at least one of the at least two substrate layers has a geoelectric layer thereon; and the metal matrix is fixed in a slot provided in the substrate, the formed hole contacts both the geoelectric layer and the metal matrix; and providing conductive substances in the hole, with the conductive substances in the hole being in contact with the inner geoelectric layer and the metal matrix, so that the geoelectric layer and the metal matrix are in conduction with each other.

Abstract translation: 印刷电路板（PCB），PCB的处理方法和电子设备。 用于处理PCB的方法可以包括：在PCB中形成孔，其中PCB包括金属基体和至少两个基底层，至少两个基底层中的至少一个在其上具有地电层; 并且所述金属基体固定在设置在所述基板中的槽内，所形成的孔与所述地电电极层和所述金属基体接触; 并且在孔中提供导电物质，孔中的导电物质与内部地电电极和金属基体接触，使得地电电介质层和金属基体彼此导通。

公开(公告)号：US20150107884A1

公开(公告)日：2015-04-23

申请号：US14391748

申请日：2013-02-28

Applicant: KABUSHIKI KAISHA NIHON MICRONICS

Inventor： Tatsuo Inoue ,  Takayasu Sugai ,  Toshiyuki Kudo ,  Toshinori Omori

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/09

CPC classification number: H05K1/0298 ,  H05K1/0233 ,  H05K1/0242 ,  H05K1/025 ,  H05K1/09 ,  H05K3/46 ,  H05K2201/0154 ,  H05K2201/0338 ,  H05K2201/0391 ,  H05K2201/0776 ,  H05K2201/0792 ,  H05K2201/083 ,  Y10T29/49155

Abstract: The object of the present invention is to provide a multi-layer wiring board which is easy to adjust the characteristic impedance and is able to adapt to the narrow-pitch tendency of terminals, and a process for manufacturing the same.The present invention attain the object by providing a multi-layer wiring board, in which more than one wiring layers are stacked on a substrate with an insulating layer between them, wherein a wire formed in the wiring layer has a double layered structure consists of a first layer and a second layer, and said first layer is made of a first conductive material and said second layer is made of a second conductive material having relative magnetic permeability larger than that of the first conductive material, thereby the characteristic impedance of said wire is adjusted to a value closer to 50 ohm than that of a wire which has the same thickness as of said wire having the double layered structure, and is made of said first conductive material only, and a process for manufacturing the same.

Abstract translation: 本发明的目的是提供一种容易调节特性阻抗并能够适应端子的窄倾斜趋势的多层布线板及其制造方法。 本发明的目的在于提供一种多层布线基板，其中多个布线层层叠在基板之间，在它们之间具有绝缘层，其中形成在布线层中的布线具有双层结构， 第一层和第二层，并且所述第一层由第一导电材料制成，并且所述第二层由具有比第一导电材料的相对导磁率大的相对磁导率的第二导电材料制成，由此所述导线的特征阻抗 调整为比具有与具有双层结构的所述线具有相同厚度的导线的接近50欧姆的值，并且仅由所述第一导电材料制成，及其制造方法。