公开(公告)号：US11769719B2

公开(公告)日：2023-09-26

申请号：US16017671

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Jonathan Rosch ,  Wei-Lun Jen ,  Cheng Xu ,  Liwei Cheng ,  Andrew Brown ,  Yikang Deng

IPC: H05K1/11 ,  H05K1/18 ,  H01L23/498 ,  H01L21/48 ,  H05K1/02

CPC classification number: H01L23/49838 ,  H01L21/486 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/111 ,  H05K1/115 ,  H05K1/025 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09827

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US11749590B2

公开(公告)日：2023-09-05

申请号：US17123668

申请日：2020-12-16

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Tatsuya Koike

IPC: H01L23/528 ,  H01L23/498 ,  H05K3/34 ,  H05K1/11 ,  H05K3/46 ,  H05K3/40

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H05K1/115 ,  H05K3/34 ,  H05K3/3452 ,  H05K3/4015 ,  H05K3/4644 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H05K2201/095 ,  H05K2201/098 ,  H05K2203/02 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A wiring substrate device includes a wiring substrate, a plurality of terminals each of which is provided upright on the wiring substrate and has a lower end, an upper end and a narrowed part between the lower end and the upper end, and a plurality of solders each of which has a melting point lower than the terminals and covers a surface of the corresponding terminal.

公开(公告)号：US20180139852A1

公开(公告)日：2018-05-17

申请号：US15351066

申请日：2016-11-14

Applicant: International Business Machines Corporation

Inventor： Bruce J. CHAMBERLIN ,  Scott B. KING ,  Joseph KUCZYNSKI ,  David J. RUSSELL

IPC: H05K3/40 ,  H05K3/22 ,  H05K3/46 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K3/4076 ,  H05K1/09 ,  H05K1/116 ,  H05K3/002 ,  H05K3/0038 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/09581 ,  H05K2203/0723 ,  H05K2203/0793 ,  H05K2203/10 ,  H05K2203/11 ,  H05K2203/1184

Abstract: In some embodiments, methods include drilling one or a plurality of PTHs with any industrial grade drill to fabricate holes with positive etch back, flooding the PTHs with a dilute solution of an acrylate monomer/oligomer containing an appropriate level of peroxide initiator, polymerizing the acrylate, and then rising the PTHs with the solvent used in the formulation of the acrylate material. In one embodiment, the printed circuit board may include a substrate comprising a plurality of metal layers separated by a plurality of insulating layers; a plurality of plated through holes formed in the substrate, each plated through hole comprising: recesses formed at each insulating layer, copper lands between the recesses, a polymer coating in each recess, and a metal layer lining the plated through hole.

公开(公告)号：US09832863B2

公开(公告)日：2017-11-28

申请号：US14866614

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Shawna Liff

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/22 ,  H05K3/30 ,  H05K1/03

CPC classification number: H05K1/028 ,  H05K1/0283 ,  H05K1/0393 ,  H05K1/115 ,  H05K1/118 ,  H05K1/181 ,  H05K3/22 ,  H05K3/284 ,  H05K3/301 ,  H05K3/4691 ,  H05K2201/05 ,  H05K2201/057 ,  H05K2201/09263 ,  H05K2201/095 ,  H05K2203/1316

Abstract: Some forms relate to a stretchable computing device that includes a stretchable body; a first electronic component embedded within the stretchable body; a second electronic component embedded within the stretchable body; and wherein the first electronic component and the second electronic component are connected by stretchable electrical connectors that include vias. The stretchable electrical connectors are non-planar and/or may have a partial zig-zag shape and/or a partial coil shape. In some forms, the stretchable computing device further includes a textile attached to the stretchable body.

公开(公告)号：US20170339795A1

公开(公告)日：2017-11-23

申请号：US15191554

申请日：2016-06-24

Applicant: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd. ,  FuKui Precision Component (Shenzhen) Co., Ltd. ,  Zhen Ding Technology Co., Ltd.

Inventor： YAN-LU LI ,  MEI YANG ,  CHENG-JIA LI

IPC: H05K3/46 ,  H05K3/40 ,  H05K1/09 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/02

CPC classification number: H05K3/4644 ,  H05K1/0298 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/0073 ,  H05K3/02 ,  H05K3/4038 ,  H05K2201/095

Abstract: A method of manufacture of a circuit board without annular through-hole rings and thus allowing a higher component density includes a base layer, a first wire pattern layer, and a second wire pattern layer on both sides of the base layer. A portion of the base layer not covered by the first wire pattern layer defines at least one first hole. The circuit board further includes a wire layer. The wire layer includes at least a first portion and a second portion connecting to the first portion. The first portion is filled in the first hole. The second portion is formed on the first portion extending away from the base layer. A diameter of the second portion is less than an aperture diameter of the first hole. The wire layer is electrically conductive between the first wire pattern layer and the second wire pattern layer through the first portion.

公开(公告)号：US09795026B2

公开(公告)日：2017-10-17

申请号：US14969514

申请日：2015-12-15

Applicant: Intel Corporation

Inventor： Nayandeep K. Mahanta ,  Joshua D. Heppner ,  Adel A. Elsherbini

IPC: H05K1/02 ,  H05K1/18 ,  H05K1/11

CPC classification number: H05K1/0206 ,  H01L23/34 ,  H05K1/115 ,  H05K1/18 ,  H05K2201/095 ,  H05K2201/09854

Abstract: The electronic package includes a substrate that includes a plurality of dielectric layers and conductive routings between the plurality of dielectric layers; wherein the substrate further includes a plurality of thermal finned vias that electrically connect the conductive routings within the substrate to one another; and an electronic component mounted on the substrate, wherein the finned via transfers heat from the electronic component to the substrate and electrically connects the conductive routings within the substrate to the electronic component.

公开(公告)号：US20160278207A1

公开(公告)日：2016-09-22

申请号：US14834180

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/06 ,  H05K3/42 ,  H05K1/02 ,  H05K3/00

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

Abstract translation: 用于制造电路板的选择性段通过电镀工艺选择性地将内部导电层互连在相同的通孔内的单独的段。 电镀抗蚀剂插入内芯通孔，然后在化学镀处理后剥离。 在电镀抗蚀剂上剥离化学镀导致通孔壁上的电镀不连续。 在随后的电镀工艺中，由于电镀不连续，内芯层不能镀覆。 所得到的电路板结构在通孔内具有单独的电互连段。

公开(公告)号：US20160143140A1

公开(公告)日：2016-05-19

申请号：US14860718

申请日：2015-09-22

Applicant: Mediatek Inc.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

Abstract translation: 印刷电路板包括至少包括内部导电层和层压芯上的堆积层的叠层芯。 堆积层包括顶部导电层。 多个微孔设置在积层层中以将顶部导电层与内部导电层电连接。 电源/接地球垫阵列设置在顶部导电层中。 电源/接地球垫阵列包括排列成具有固定球垫间距P的阵列的功率球垫和接地球垫。电源/接地球垫阵列包括仅由一个接地球组成的4球垫单元区域 垫和三个电源球垫，或仅由一个电源球垫和三个地球垫组成。 四球垫单位面积为矩形，尺寸约为2P×2P。

公开(公告)号：US20160105961A1

公开(公告)日：2016-04-14

申请号：US14894558

申请日：2014-05-27

Applicant: LINXENS HOLDING

Inventor： Severine DIEU-GOMONT ,  Bertrand HOVEMAN

IPC: H05K1/11 ,  H05K3/06 ,  H05K3/28 ,  H05K1/02

CPC classification number: H01L24/85 ,  G06K19/07769 ,  H01L23/49855 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49 ,  H01L2224/49109 ,  H01L2224/85 ,  H01L2224/85002 ,  H01L2924/00014 ,  H05K1/028 ,  H05K1/0296 ,  H05K1/11 ,  H05K1/115 ,  H05K3/06 ,  H05K3/28 ,  H05K2201/0394 ,  H05K2201/095 ,  H05K2201/09509 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: The invention concerns a method for producing a printed circuit for a chip card module. This method involves producing two layers of electrically conductive material insulated from each other by a layer of insulating material, connection holes extending through the layer of insulating material and blocked by one of the layers of electrically conductive material, an area free of conductive material being provided in the other layer of electrically conductive material around the connection holes. The invention also concerns a printed circuit for a chip card produced using this method and a chip card module including such a printed circuit.

Abstract translation: 本发明涉及一种用于制造用于芯片卡模块的印刷电路的方法。 该方法包括通过绝缘材料层彼此绝缘的两层导电材料制成，连接孔延伸穿过绝缘材料层并被导电材料层之一阻挡，提供了不含导电材料的区域 在连接孔周围的另一层导电材料中。 本发明还涉及使用该方法制造的芯片卡的印刷电路和包括这种印刷电路的芯片卡模块。

公开(公告)号：US20150271917A1

公开(公告)日：2015-09-24

申请号：US14732309

申请日：2015-06-05

Applicant: Tyco Electronics AMP Korea Ltd

Inventor： Yang Yun Choi ,  Ok Ky Beak

IPC: H05K1/02 ,  H05K3/06 ,  H05K3/46 ,  H05K1/09 ,  H05K1/11

CPC classification number: H05K1/0298 ,  C23C18/1637 ,  C23C18/1653 ,  C23C18/54 ,  C25D5/02 ,  H05K1/0206 ,  H05K1/0251 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/386 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/462 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0323 ,  H05K2201/095 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073 ,  H05K2203/1476

Abstract: A printed circuit board has a double-sided substrate with an insulation layer, a bonding member, a base layer of an aluminum material, and a circuit pattern; a second insulation layer; a second bonding member; a second base layer; a through hole; a zinc substitution layer; a plating layer; and a second circuit pattern.

Abstract translation: 印刷电路板具有带有绝缘层，接合部件，铝材料的基底层和电路图案的双面基板; 第二绝缘层; 第二接合构件; 第二基层; 一个通孔; 锌取代层; 电镀层; 和第二电路图案。