公开(公告)号：US20090166059A1

公开(公告)日：2009-07-02

申请号：US12048909

申请日：2008-03-14

Applicant: Tsung-Yuan Chen ,  Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  David C. H. Cheng

Inventor： Tsung-Yuan Chen ,  Tzyy-Jang Tseng ,  Shu-Sheng Chiang ,  David C. H. Cheng

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K1/0219 ,  H05K3/20 ,  H05K2201/0376 ,  H05K2201/09236 ,  H05K2201/09736 ,  Y10T29/49155

Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, a main circuit, and two shielding circuits. The dielectric layer has an active surface. The main circuit is embedded in the dielectric layer and the shielding circuits are disposed at the dielectric layer. The shielding circuits are respectively located at two sides of the main circuit. The thickness of the shielding circuits is larger than the thickness of the main circuit.

Abstract translation: 提供电路板及其工艺。 电路板包括电介质层，主电路和两个屏蔽电路。 电介质层具有活性表面。 主电路嵌入电介质层，屏蔽电路设置在电介质层。 屏蔽电路分别位于主电路的两侧。 屏蔽电路的厚度大于主电路的厚度。

公开(公告)号：US20090155959A1

公开(公告)日：2009-06-18

申请号：US11958603

申请日：2007-12-18

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Kang Chen ,  Jianmin Fang

IPC: H01L21/50

CPC classification number: H01L23/50 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/48 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/20 ,  H05K3/4602 ,  H05K2201/0352 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/09736 ,  H05K2203/016 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of manufacturing a semiconductor device includes providing a substrate with an insulation layer disposed on a top surface of the substrate, forming a passive device over the top surface of the substrate, removing the substrate, depositing an insulating polymer film layer over the insulation layer, and depositing a metal layer over the insulating polymer film layer. A solder mask can be formed over the metal layer. A conformal metal layer can then be formed over the solder mask. A notch can be formed in the insulation layer to enhance the connection between the insulating polymer film layer and the insulation layer. Additional semiconductor die can be electrically connected to the passive device. The substrate is removed by removing a first amount of the substrate using a back grind process, and then removing a second amount of the substrate using a wet dry, dry etch, or chemical-mechanical planarization process.

Abstract translation: 一种制造半导体器件的方法包括：在衬底的顶表面上设置绝缘层，在衬底的顶表面上形成无源器件，去除衬底，在绝缘层上沉积绝缘聚合物膜层 并且在绝缘聚合物膜层上沉积金属层。 可以在金属层上形成焊接掩模。 然后可以在焊接掩模上形成保形金属层。 可以在绝缘层中形成切口以增强绝缘聚合物膜层和绝缘层之间的连接。 另外的半导体管芯可以电连接到无源器件。 通过使用后研磨工艺去除第一量的基材，然后使用湿干，干蚀刻或化学机械平面化工艺除去第二量的基材来除去基材。

公开(公告)号：US20090128993A1

公开(公告)日：2009-05-21

申请号：US12173032

申请日：2008-07-15

Applicant: Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shur-Fen Liu

Inventor： Shih-Hsien Wu ,  Min-Lin Lee ,  Shinn-Juh Lai ,  Shur-Fen Liu

IPC: H01G4/38

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01G4/38 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/162 ,  H05K3/243 ,  H05K3/4611 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09736 ,  H05K2201/09845 ,  H01L2924/00

Abstract: A multi-tier capacitor structure has at least one multi-tier conductive layer. At least one conductive via passes through the multi-tier conductive layer. When currents flow through the conductive via, different current paths are presented in the conductive via in response to different current frequency; in other words, different inductor is induced. Therefore, a single plate capacitor structure has function of hierarchical decoupling capacitor effect.

Abstract translation: 多层电容器结构具有至少一个多层导电层。 至少一个导电通孔穿过多层导电层。 当电流流过导电通孔时，响应于不同的电流频率，在导电通孔中呈现不同的电流路径; 换句话说，感应不同的电感。 因此，单板电容器结构具有分层去耦电容效应的功能。

公开(公告)号：US20090039490A1

公开(公告)日：2009-02-12

申请号：US11889018

申请日：2007-08-08

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/12

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/49838 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/09136 ,  H05K2201/094 ,  H05K2201/09736 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A mounting assembly of semiconductor packages is revealed, primarily comprising at least a semiconductor package having a plurality of external terminals, a package carrier, and solder paste. The solder paste joints the external terminals to the package carrier. According to the distance to a central line on a substrate of the semiconductor package, the external terminals are divided into at least two different groups. In one of the embodiment, different groups of the external terminals are bumps with non-equal heights to achieve a uniform standoff plane to compensate the warpage of the substrate. The predicted substrate warpage can be compensated without causing any soldering defects. In another embodiment, a plurality of compensating bumps are selectively disposed on one group of the external terminals with larger stacking gaps.

Abstract translation: 揭示了半导体封装的安装组件，主要包括至少具有多个外部端子的半导体封装，封装载体和焊膏。 焊膏将外部端子连接到封装载体。 根据与半导体封装的基板上的中心线的距离，将外部端子划分为至少两个不同的组。 在一个实施例中，不同组的外部端子是具有不相等高度的凸块，以实现均匀的支座平面以补偿基板的翘曲。 可以补偿预测的基板翘曲而不引起任何焊接缺陷。 在另一个实施例中，多个补偿凸块选择性地设置在具有较大堆积间隙的一组外部端子上。

公开(公告)号：US07488675B2

公开(公告)日：2009-02-10

申请号：US11684583

申请日：2007-03-09

Applicant: Ting-Hao Lin

Inventor： Ting-Hao Lin

IPC: H01L21/44

CPC classification number: H05K1/116 ,  H05K3/064 ,  H05K3/427 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09736 ,  Y10T29/41 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating an IC board without a ring structure is provided. In the method, after the completion of the core board (including the core through hole), the second pattern photoresist layer is used to mask over the first deposited metal layer, and a portion of the second deposited metal layer (this portion of the second deposited metal layer is to electrically couple to the conductive circuit of the core through hole). Later, the second deposited metal layer, the first deposited metal layer, the metal layer, and the substrate at the innermost layer which are not masked by the second pattern photoresist layer are removed. As a result, the substrate is exposed to form the ringless structure, and to couple a conductive line to the core board through hole.

Abstract translation: 提供一种制造没有环形结构的IC板的方法。 在该方法中，在芯板（包括芯通孔）完成之后，第二图案光致抗蚀剂层用于掩蔽第一沉积金属层，并且第二沉积金属层的一部分（第二次 沉积的金属层电连接到芯通孔的导电电路）。 然后，去除未被第二图案光刻胶层掩蔽的第二沉积金属层，第一沉积金属层，金属层和最内层的基板。 结果，基板被暴露以形成无环结构，并且将导电线耦合到芯板通孔。

公开(公告)号：US20090008136A1

公开(公告)日：2009-01-08

申请号：US12213868

申请日：2008-06-25

Applicant: Nobuyuki Ikeguchi ,  Keungjin Sohn ,  Joon-Sik Shin

Inventor： Nobuyuki Ikeguchi ,  Keungjin Sohn ,  Joon-Sik Shin

IPC: H05K1/03 ,  H05K3/02

CPC classification number: H05K1/0271 ,  H01L23/5383 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/4602 ,  H05K3/4641 ,  H05K3/4652 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/0352 ,  H05K2201/068 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2201/10674 ,  H05K2203/061 ,  Y10T29/49149 ,  Y10T29/49155 ,  H01L2224/05599

Abstract: A multilayered printed circuit board and a method of fabricating the printed circuit board are disclosed. The method of fabricating the multilayered printed circuit board can include: providing a core substrate, which has an outer circuit, and which has a thermal expansion coefficient of 10 to 20 ppm/° C. at −60 to 150° C.; stacking a stress-relieving insulation layer, which has a thermal expansion coefficient of −20 to 6 ppm/° C., on either side of the core substrate; and forming a metal layer on the insulation layer and forming at least one pad and electrically connecting the pad with the outer circuit. This method can provide high reliability, as the stress-relieving insulation layers can prevent bending and warpage, etc., in the board overall.

Abstract translation: 公开了一种多层印刷电路板和制造印刷电路板的方法。 制造多层印刷电路板的方法可以包括：提供具有外部电路的芯基板，并且在-60至150℃下具有10至20ppm /℃的热膨胀系数; 在芯基板的两侧堆叠热膨胀系数为-20〜6ppm /℃的应力消除绝缘层; 以及在所述绝缘层上形成金属层并且形成至少一个焊盘并将所述焊盘与所述外部电路电连接。 该方法可以提供高可靠性，因为应力消除绝缘层可以防止板的弯曲和翘曲等。

公开(公告)号：US20080264676A1

公开(公告)日：2008-10-30

申请号：US11976207

申请日：2007-10-22

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/00

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US20080216313A1

公开(公告)日：2008-09-11

申请号：US11684583

申请日：2007-03-09

Applicant: Ting-Hao Lin

Inventor： Ting-Hao Lin

IPC: H05K3/10

CPC classification number: H05K1/116 ,  H05K3/064 ,  H05K3/427 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2201/09736 ,  Y10T29/41 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for fabricating an IC board without a ring structure is provided, in which after the completion of the core board (including the core through hole), the second pattern photoresist layer is used to mask over the first depositing metal layer, and portion of the second depositing metal layer (this portion of the second depositing metal layer is to electrically couple to the conductive circuit of the core through hole). Later, the second depositing metal layer, the first depositing metal layer, the metal layer, and even to the substrate at the innermost layer which are for the portion that are not masked by the second pattern photoresist layer are removed. As a result, the substrate is exposed to form the ringless structure, but which is to couple a conductive line to the core board through hole.

Abstract translation: 提供一种用于制造没有环形结构的IC板的方法，其中在芯板（包括芯通孔）完成之后，使用第二图案光致抗蚀剂层来掩蔽第一沉积金属层，并将部分 第二沉积金属层（第二沉积金属层的该部分电耦合到芯通孔的导电电路）。 之后，去除第二沉积金属层，第一沉积金属层，金属层，甚至去除未被第二图案光刻胶层掩蔽的部分的最内层的基板。 结果，基板被暴露以形成无环结构，但是将导电线耦合到芯板通孔。

公开(公告)号：US20080106209A1

公开(公告)日：2008-05-08

申请号：US12000167

申请日：2007-12-10

Applicant: Takaaki Hayashi

Inventor： Takaaki Hayashi

IPC: G09G3/12

CPC classification number: H01L27/3276 ,  G02F1/13452 ,  G02F2001/13456 ,  G09G2300/0426 ,  H01L27/3223 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K1/117 ,  H05K3/222 ,  H05K3/361 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/10128 ,  H05K2201/10681 ,  H01L2924/00

Abstract: An electronic module includes an EL section; a first substrate on which the EL section is formed; a second substrate attached to the first substrate; an integrated circuit chip mounted on the second substrate; a plurality of first power supply interconnects formed on the first substrate, extending through a pair of regions located on both sides of the EL section; and a plurality of second power supply interconnects formed on the second substrate, extending through a pair of regions located on both sides of the integrated circuit chip.

Abstract translation: 电子模块包括EL部分; 形成有EL部的第一基板; 附接到所述第一基板的第二基板; 安装在所述第二基板上的集成电路芯片; 多个第一电源互连，形成在第一基板上，延伸穿过位于EL部分两侧的一对区域; 以及多个第二电源互连，形成在第二基板上，延伸穿过位于集成电路芯片两侧的一对区域。

公开(公告)号：US07368998B2

公开(公告)日：2008-05-06

申请号：US11608609

申请日：2006-12-08

Applicant: Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

Inventor： Toshiyuki Abe ,  Yoshihiro Suzuki ,  Masashi Katsumata

IPC: H03F3/14 ,  H03H7/00

CPC classification number: H05K1/0265 ,  H01L2924/1423 ,  H03F3/195 ,  H03F2200/294 ,  H05K1/165 ,  H05K3/243 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2201/09881 ,  H05K2203/0542

Abstract: An inductor element containing circuit board of the present invention comprises a plurality of conductive layers, and a conductor having an inductor function (inductor conductor segment) in one or more of the conductive layers, wherein at least part of the inductor conductor segment is made thicker than other conductors disposed within the circuit board. The at least part of the inductor conductor segment extends through an insulating layer disposed between the conductive layers, or is embedded in the insulating layer, wherein the part of the inductor conductor segment has a thickness one-half or more the thickness of the insulating layer. A power amplifier module of the present invention comprises the multi-layer circuit board, a semiconductor amplifier fabricated in the multi-layer circuit board, and an impedance matching circuit coupled to the output of the semiconductor amplifier. The impedance matching circuit has a portion thereof formed of the inductor conductor segment.

Abstract translation: 本发明的电感器元件电路板包括多个导电层，以及在一个或多个导电层中具有电感器功能（电感器导体段）的导体，其中电感器导体段的至少一部分变厚 而不是设置在电路板内的其它导线。 电感器导体段的至少一部分延伸穿过设置在导电层之间的绝缘层，或者嵌入在绝缘层中，其中电感器导体段的一部分具有绝缘层的厚度的一半或更多的厚度 。 本发明的功率放大器模块包括多层电路板，在多层电路板中制造的半导体放大器和耦合到半导体放大器的输出的阻抗匹配电路。 阻抗匹配电路具有由电感器导体段形成的部分。