公开(公告)号：US10742224B2

公开(公告)日：2020-08-11

申请号：US16382050

申请日：2019-04-11

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Sanquan Song

IPC: H03L7/099 ,  H03K3/03 ,  H03L7/07 ,  H03K5/133

Abstract: A circuit includes a first ring oscillator with a plurality of stages, each coupled via a voltage follower cross-coupling to a plurality of stages of a second ring oscillator. Further ring oscillators may be coupled to the first ring oscillator and the second ring oscillator. Additionally, the voltage follower cross-coupling for each of the stages may include one or more first voltage follower having a first strength, and one or more second voltage follower having a second strength different than the first strength.

公开(公告)号：US20200210276A1

公开(公告)日：2020-07-02

申请号：US16811499

申请日：2020-03-06

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Hari ,  Brian Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/10 ,  G06F11/07 ,  G06F9/30

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

公开(公告)号：US20200151289A1

公开(公告)日：2020-05-14

申请号：US16537376

申请日：2019-08-09

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06F17/50 ,  G06N3/08 ,  G06N3/04 ,  G06K9/62 ,  G06N7/00

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US10581645B1

公开(公告)日：2020-03-03

申请号：US16427138

申请日：2019-05-30

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  Nikola Nedovic

IPC: H04L25/03 ,  H03K19/0185 ,  H04B1/40 ,  H03F3/45

Abstract: A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.

公开(公告)号：US20200021983A1

公开(公告)日：2020-01-16

申请号：US16034635

申请日：2018-07-13

Applicant: NVIDIA Corp.

Inventor： Nagaraj Annaiah ,  Om Prakash Singh

IPC: H04W12/06 ,  H04L29/12 ,  H04L29/08

Abstract: A method involves a headless IoT device wirelessly communicating a MAC address to a client device in response to a scan by the client device, and receiving from the client device a vendor action frame comprising access credentials for communicating via a Wi-Fi access point. The IoT device applies the credentials to authenticate to the Wi-Fi access point, forms an application layer for communicating over the Wi-Fi access point network, and communicates with the client device via the application layer.

公开(公告)号：US20190340728A1

公开(公告)日：2019-11-07

申请号：US16130871

申请日：2018-09-13

Applicant: NVIDIA Corp.

Inventor： Varun Jampani ,  Deqing Sun ,  Ming-Yu Liu ,  Jan Kautz

IPC: G06T3/40 ,  G06T7/10 ,  G06N3/08 ,  G06K9/62

Abstract: A superpixel sampling network utilizes a neural network coupled to a differentiable simple linear iterative clustering component to determine pixel-superpixel associations from a set of pixel features output by the neural network. The superpixel sampling network computes updated superpixel centers and final pixel-superpixel associations over a number of iterations.

公开(公告)号：US10466968B1

公开(公告)日：2019-11-05

申请号：US16033468

申请日：2018-07-12

Applicant: NVIDIA Corp.

Inventor： Ilyas Elkin

IPC: G06F7/523 ,  G06F7/49

Abstract: A system including a series of partial product select encoders and partial product muxes, each of the partial product select encoders receiving a multiplier, receiving a carry input from a multiplier tree, and outputting a select signal to an associated partial product mux based on the multiplier and carry input, and each of the partial product muxes outputting a partial product based on the select signal and a multiplicand received.

公开(公告)号：US10436840B2

公开(公告)日：2019-10-08

申请号：US15935438

申请日：2018-03-26

Applicant: NVIDIA Corp.

Inventor： Jau Wu ,  Saurabh Gupta

IPC: G01R31/3185

Abstract: A distributed test circuit includes partitions arranged in series to form a scan path, each partition including a scan multiplexer, a test data register, and a segment insertion bit component. The scan multiplexer of each partition provides inputs to the corresponding test data register of the each partition. Broadcast control logic generates a select signal to the scan multiplexer of each partition to place the test circuit in a broadcast mode when the select signal is asserted, and to switch the test circuit to a daisy mode when select signal is de-asserted. The segment insertion bit is operable to include or bypass each partition from the scan path.

公开(公告)号：US20190305765A1

公开(公告)日：2019-10-03

申请号：US16295886

申请日：2019-03-07

Applicant: NVIDIA Corp.

Inventor： Donghyuk Lee ,  James Michael O'Connor ,  John Wilson

IPC: H03K7/02 ,  H04B14/02 ,  G06F13/42

Abstract: Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.

公开(公告)号：US10404505B1

公开(公告)日：2019-09-03

申请号：US16172489

申请日：2018-10-26

Applicant: NVIDIA Corp.

Inventor： John Wilson

IPC: H04L27/04 ,  H03K19/177 ,  H04N19/184

Abstract: A system comprising a PAM-4 transmitter coupled data lanes includes a least significant bit section and a most significant bit section for the symbols generated on each lane. A controller to determine a state of the PAM-4 transmitter and selectively inverts a polarity of the symbol bits on the lanes based on the state.