公开(公告)号：US20090032921A1

公开(公告)日：2009-02-05

申请号：US12181838

申请日：2008-07-29

Applicant: Yuichi Koga

Inventor： Yuichi Koga

IPC: H01L23/495

CPC classification number: H05K1/181 ,  H01L2924/0002 ,  H05K1/0231 ,  H05K1/0243 ,  H05K2201/09481 ,  H05K2201/0949 ,  H05K2201/096 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: According to one embodiment, a printed wiring board structure includes first and second semiconductor packages each including a substrate, and a printed wiring board including first and second component mounting surfaces having a relationship given as front and back surfaces and an inter-chip connection part provided at one portion thereof, the inter-chip connection part being provided with a plurality of arrayed through conductors penetrating through the first and second component mounting surfaces, wherein the substrates of the first and second semiconductor packages are arranged on the printed wiring board in a positional relationship such that the substrates mounted on the component mounting surfaces are partially overlapped via the printed wiring board, the external connection electrodes provided on the substrates are arrayed on the overlapped portion and are conductively connected to the through conductors arrayed in the inter-chip connection part.

Abstract translation: 根据一个实施例，印刷电路板结构包括每个包括基板的第一和第二半导体封装，以及包括具有作为前后表面的关系的第一和第二元件安装表面的印刷布线板和设置有芯片间连接部分 芯片间连接部分的一部分设置有穿过第一和第二部件安装表面的多个阵列贯通导体，其中第一和第二半导体封装的基板以位置布置在印刷电路板上 关系使得安装在部件安装表面上的基板经由印刷电路板部分地重叠，设置在基板上的外部连接电极排列在重叠部分上，并且导体连接到排列在芯片间连接部分中的贯通导体 。

公开(公告)号：US20090025972A1

公开(公告)日：2009-01-29

申请号：US12087083

申请日：2006-11-20

Applicant: Katsuitsu Nishida ,  Kazuo Kinoshita

Inventor： Katsuitsu Nishida ,  Kazuo Kinoshita

IPC: H05K1/11 ,  G03B17/00 ,  B23K31/02

CPC classification number: H05K3/3494 ,  H01L2224/81224 ,  H05K1/141 ,  H05K3/0058 ,  H05K3/3442 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09781 ,  H05K2201/10121 ,  H05K2201/2009 ,  H05K2201/2054 ,  H05K2203/0557 ,  H05K2203/1581 ,  H05K2203/304

Abstract: A camera module structure (100) of the present invention is arranged such that a heat-sensitive camera module (2) is joined to a printed wiring board (1) through solder joint sections (3). The printed wiring board (1) has through holes (11) formed therein and terminals (12) formed thereon so as to close front surface apertures which are formed by the through holes (11) in the mounting surface of the printed wiring board (1). The solder joint sections (3) are provided on the terminals (12), respectively. The solder joint sections (3) are formed by heating by light (heat rays) applied to the rear side of the printed wiring board (1) by way of the terminals (12) on the printed wiring board (1), so that heat is not transmitted to the camera module (2). Accordingly, the camera module structure (100) mounted on the printed wiring board (1) is realized without heat damage to the heat-sensitive camera module (2).

Abstract translation: 本发明的相机模块结构（100）被布置成使得热敏相机模块（2）通过焊接部分（3）接合到印刷线路板（1）。 印刷电路板（1）具有形成在其中的通孔（11）和形成在其上的端子（12），以便封闭由印刷电路板（1）的安装表面中的通孔（11）形成的前表面孔 ）。 焊接部分（3）分别设置在端子（12）上。 通过在印刷电路板（1）上的端子（12）施加到印刷电路板（1）的后侧的光（热射线）加热形成焊接部分（3），使得热量 不发送到相机模块（2）。 因此，安装在印刷电路板（1）上的相机模块结构（100）实现为对热敏相机模块（2）的热损伤。

公开(公告)号：US20090013528A1

公开(公告)日：2009-01-15

申请号：US12212927

申请日：2008-09-18

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R43/16

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cros s-section and is constituted of a dielectric elastomeric material. At least one sidewall of the interposer is slitted to facilitate the venting of gases and pressure therethrough. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

Abstract translation: 一种制造包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入件的方法。 插入件在横向横截面中具有半环形结构，并由介电弹性体材料构成。 插入器的至少一个侧壁被切割以便于气体的排出和通过其中的压力。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机

公开(公告)号：US20090007427A1

公开(公告)日：2009-01-08

申请号：US12207713

申请日：2008-09-10

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R43/20

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A method of producing a land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane.

公开(公告)号：US07446403B2

公开(公告)日：2008-11-04

申请号：US11452531

申请日：2006-06-14

Applicant: Julian Partridge

Inventor： Julian Partridge

IPC: H01L23/02 ,  H05K7/00 ,  H01R12/04

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K3/429 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/2018 ,  H01L2924/00

Abstract: The present invention provides a system and method for selectively stacking and interconnecting leaded packaged integrated circuit devices with connections between the feet of leads of an upper IC and the upper shoulder of leads of a lower IC while conductive transits that implement stacking-related intra-stack connections between the constituent ICs are implemented in multi-layer interposers or carrier structures oriented along the leaded sides of the stack, with selected ones of the conductive transits electrically interconnected with other selected ones of the conductive transits.

Abstract translation: 本发明提供了一种系统和方法，用于选择性地堆叠和互连带引线的封装集成电路器件，其具有上IC的引线的脚与下IC的引线的上肩之间的连接，而实现堆叠相关的堆叠内的导电性转换 组成IC之间的连接在沿着堆叠的引导侧定向的多层插入件或载体结构中实现，其中选定的导电转移与其它选定的导电转换电互连。

公开(公告)号：US20080191345A1

公开(公告)日：2008-08-14

申请号：US11673558

申请日：2007-02-09

Applicant: Guichea Na ,  Soohan Park ,  Gwangjin Kim

Inventor： Guichea Na ,  Soohan Park ,  Gwangjin Kim

IPC: H01L23/48 ,  H01L21/44

CPC classification number: H05K3/4007 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/098 ,  H05K2201/09854 ,  H05K2203/0733

Abstract: An integrated circuit package system includes a substrate, forming a resist layer having an elongated recess over the substrate, forming a via in the substrate below the elongated recess, and forming an elongated bump in the elongated recess over the via.

Abstract translation: 集成电路封装系统包括衬底，形成在衬底上具有细长凹槽的抗蚀剂层，在细长凹槽下方的衬底中形成通孔，以及在通孔上的细长凹槽中形成细长凸点。

公开(公告)号：US20080176418A1

公开(公告)日：2008-07-24

申请号：US11865396

申请日：2007-10-01

Applicant: Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

Inventor： Gareth G. Hougham ,  Brian S. Beaman ,  Evan G. Colgan ,  Paul W. Coteus ,  Stefano S. Oggioni ,  Enrique Vargas

IPC: H01R12/00

CPC classification number: H01R12/714 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01R12/52 ,  H05K3/326 ,  H05K3/4007 ,  H05K7/1061 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09745 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49002 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49158 ,  Y10T29/49165 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/49213 ,  Y10T29/49218 ,  Y10T29/49222 ,  H01L2924/00

Abstract: A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

Abstract translation: 包括电绝缘载体平面的平面栅格阵列（LGA）插入器结构以及安装在所述载体平面的第一表面上的至少一个插入器。 插入件在横截面中具有半环形结构，并由介电弹性体材料构成。 多个导电元件围绕至少一个半环形插入器的表面布置并且从其最上端向内和向下自由地延伸至与位于电绝缘载体的相对侧上的至少一个部件的电接触 飞机 还提供了一种制造焊盘栅格阵列中介层结构的方法。

公开(公告)号：US20080149732A1

公开(公告)日：2008-06-26

申请号：US11673596

申请日：2007-02-12

Applicant: Hsing-Lun Lo ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

Inventor： Hsing-Lun Lo ,  Hsien-Chieh Lin ,  Kuo-Chun Chiang ,  Shing-Fun Ho

IPC: G06K19/067

CPC classification number: H05K1/0266 ,  H05K1/0268 ,  H05K2201/09481 ,  H05K2201/09927

Abstract: A lot traceable printed circuit board (PCB) includes a substrate having thereon a patterned circuit layer and a working zone carrying production information related to the PCB itself. The working zone includes a plurality of code boxes, wherein each of the code boxes has a first probe region and second probe region. A single set of resistance test loop is disposed within the first probe region. Four sets of resistance test loops are disposed within the second probe region. A frying probe tester is used to probe the set of resistance test loops respectively for abstracting the production information recorded in the working zone.

Abstract translation: 许多可追溯的印刷电路板（PCB）包括其上具有图案化电路层的基板和承载与PCB本身相关的生产信息的工作区。 工作区域包括多个代码框，其中每个代码框具有第一探测区域和第二探测区域。 单个电阻测试环路设置在第一探测区域内。 四组电阻测试环设置在第二探针区域内。 使用油炸探针测试仪分别探测一组电阻测试回路，以抽取记录在工作区域中的生产信息。

公开(公告)号：US20080145622A1

公开(公告)日：2008-06-19

申请号：US11610601

申请日：2006-12-14

Applicant: Mihir K. Roy ,  Islam A. Salama ,  Yongki Min

Inventor： Mihir K. Roy ,  Islam A. Salama ,  Yongki Min

IPC: B05D5/12 ,  B32B9/04 ,  B32B3/10

CPC classification number: H01G4/18 ,  H01G4/33 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15313 ,  H05K1/162 ,  H05K3/108 ,  H05K3/429 ,  H05K2201/015 ,  H05K2201/0187 ,  H05K2201/0209 ,  H05K2201/09481 ,  H05K2201/10674 ,  H05K2203/0568 ,  H05K2203/121 ,  Y10T428/24802

Abstract: Some embodiments include thin film capacitors (TFC) formed on a package substrate of an integrated circuit package. The TFC include a polymer-based dielectric layer deposited directly on the package substrate. At least one of the TFC includes a first electrode layer, a second electrode layer, with the polymer-based dielectric layer located between the first and second electrode layers. Each of the first and second electrode layers is also formed individually and directly on the package substrate. Other embodiments are described and claimed.

Abstract translation: 一些实施例包括形成在集成电路封装的封装衬底上的薄膜电容器（TFC）。 TFC包括直接沉积在封装衬底上的基于聚合物的电介质层。 TFC中的至少一个包括第一电极层，第二电极层，聚合物基电介质层位于第一和第二电极层之间。 第一和第二电极层中的每一个也单独形成并且直接在封装衬底上形成。 描述和要求保护其他实施例。

公开(公告)号：US20080137263A1

公开(公告)日：2008-06-12

申请号：US11609295

申请日：2006-12-11

Applicant: Yongki Min ,  Huankiat Seh

Inventor： Yongki Min ,  Huankiat Seh

IPC: H01G4/06 ,  H01L21/62

CPC classification number: H01G4/33 ,  H01G4/232 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L27/016 ,  H01L2924/0002 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09309 ,  H05K2201/09481 ,  H05K2201/09518 ,  H05K2201/09718 ,  H05K2203/1184 ,  Y10S438/957 ,  Y10T29/41 ,  Y10T29/417 ,  Y10T29/43 ,  H01L2924/00

Abstract: A microelectronic device, a method of fabricating the device, and a system including the device. The method includes: providing a substrate including an underlying conductive layer and a polymer build-up layer overlying the underlying conductive layer; providing a passive microelectronic structure; embedding the passive structure in the polymer build-up layer of the substrate; and patterning the passive structure after embedding, patterning including over-etching the bottom electrode layer. The passive microelectronic structure being embedded includes an unpatterned bottom electrode layer; an unpatterned capacitor dielectric layer overlying the bottom electrode layer; and an unpatterned top electrode layer overlying the capacitor dielectric layer.

Abstract translation: 微电子器件，制造该器件的方法以及包括该器件的系统。 该方法包括：提供包括下面的导电层和覆盖在下面的导电层上的聚合物堆积层的衬底; 提供无源微电子结构; 将被动结构嵌入衬底的聚合物堆积层中; 并且在嵌入之后图案化被动结构，图案化包括对底部电极层进行过蚀刻。 嵌入的被动微电子结构包括未图案化的底电极层; 覆盖底部电极层的未图案化的电容器电介质层; 以及覆盖电容器介电层的未图案化的顶部电极层。