公开(公告)号：US20090156020A1

公开(公告)日：2009-06-18

申请号：US12315305

申请日：2008-12-02

Applicant: Naoya Kitajima ,  Seiya Takahashi ,  Katsumi Arai

Inventor： Naoya Kitajima ,  Seiya Takahashi ,  Katsumi Arai

IPC: H05K1/00

CPC classification number: H05K1/118 ,  H01R12/716 ,  H01R13/2414 ,  H05K3/0058 ,  H05K3/027 ,  H05K3/365 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  H05K2201/09172 ,  H05K2201/09663 ,  H05K2203/0369

Abstract: The present invention provides a connector configured to electrically connect two connection objects. The connector comprises an elastic member having a surface and a conductive film placed on the surface of the elastic member. The conductive film comprises two contact portions to be brought into contact with the connection objects, respectively, and a connect portion connecting the contact portions. Each of the contact portions comprises projections and a drainage arranged, at least in part, between the projections.

Abstract translation: 本发明提供一种被配置为电连接两个连接对象的连接器。 连接器包括具有放置在弹性构件的表面上的表面和导电膜的弹性构件。 导电膜包括分别与连接对象接触的两个接触部分和连接接触部分的连接部分。 每个接触部分包括至少部分地在突起之间布置的突起和排水。

公开(公告)号：US20090152690A1

公开(公告)日：2009-06-18

申请号：US11956434

申请日：2007-12-14

Applicant: Yue Li ,  Silqun Leung ,  Terence Cheung ,  Sally Yeung ,  Liane Martinez

Inventor： Yue Li ,  Silqun Leung ,  Terence Cheung ,  Sally Yeung ,  Liane Martinez

IPC: H01L23/48 ,  H01L21/58

CPC classification number: H01L23/50 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/19105 ,  H05K1/0295 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09663 ,  H05K2201/099 ,  H05K2201/09954 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: Various methods and apparatus for coupling capacitors to a chip substrate are disclosed. In one aspect, a method of manufacturing is provided that includes forming a mask on a semiconductor chip substrate that has plural conductor pads. The mask has plural openings that expose selected portions of the plural conductor pads. Each of the plural openings has a footprint corresponding to a footprint of a smallest size terminal of a capacitor adapted to be coupled to the semiconductor chip substrate. A conductor material is placed in the plural openings to establish plural capacitor pads.

Abstract translation: 公开了用于将电容器耦合到芯片衬底的各种方法和装置。 一方面，提供一种制造方法，其包括在具有多个导体焊盘的半导体芯片基板上形成掩模。 该掩模具有多个露出多个导体焊盘的选定部分的开口。 多个开口中的每一个具有对应于适于耦合到半导体芯片衬底的电容器的最小尺寸端子的覆盖区的覆盖区。 将导体材料放置在多个开口中以建立多个电容器焊盘。

公开(公告)号：US20090133913A1

公开(公告)日：2009-05-28

申请号：US12089483

申请日：2006-10-10

Applicant: Taras Kushta ,  Kaoru Narita

Inventor： Taras Kushta ,  Kaoru Narita

IPC: H05K1/16 ,  H05K1/00

CPC classification number: H05K1/0222 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6622 ,  H01L2224/16235 ,  H01L2924/01004 ,  H01L2924/01057 ,  H01L2924/01087 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/115 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09618 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718

Abstract: Provided are vertical transitions which have the high electrical performance and the high shielding properties in the wide frequency band in a multilayer PCB, printed circuit boards with the vertical transitions and semiconductor packages with the printed circuit boards and semiconductor chips. In vertical transitions for a multilayer PCB, a wave guiding channel is a conductor which includes at least more than one of signal vias 201, an assembly of ground vias 202 surrounding the signal via, ground plates from conductor layers of the PCB connected to the ground vias, closed ground striplines 205 connecting the ground vias and power supply layer.

Abstract translation: 提供了在多层PCB中的宽频带中具有高电性能和高屏蔽性能的垂直转换，具有垂直转换的印刷电路板和具有印刷电路板和半导体芯片的半导体封装。 在多层PCB的垂直转换中，波导通道是包括至少多于一个信号通孔201的导体，围绕信号通孔的接地通孔202的组件，与连接到地面的PCB的导体层的接地板 通孔，连接接地通孔和电源层的闭合接地带状线205。

公开(公告)号：US07530043B2

公开(公告)日：2009-05-05

申请号：US11563158

申请日：2006-11-25

Applicant: Shou-Kuo Hsu ,  Cheng-Hong Liu

Inventor： Shou-Kuo Hsu ,  Cheng-Hong Liu

IPC: G06F17/50 ,  H05K7/08 ,  H05K1/11

CPC classification number: H05K1/0216 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09345 ,  H05K2201/09663

Abstract: A printed circuit board includes a first layer including a first power portion and a first ground portion isolated from each other, and a second layer including a second power portion and a second ground portion isolated from each other. The second layer is spaced from the first layer. The second ground portion is arranged below the first power portion. The second power portion is arranged below the first ground portion. One portion of the first power portion overlaps one portion of the second power portion, and one portion of the first ground portion overlaps one portion of the second ground portion to provide a zero-intensity electric field between the first layer and the second layer. The first power portion is coupled to the second power portion via a first via. The first ground portion is coupled to the second ground portion via a second via.

Abstract translation: 印刷电路板包括第一层，第一层包括彼此隔离的第一电力部分和第一接地部分，以及包括彼此隔离的第二电力部分和第二接地部分的第二层。 第二层与第一层间隔开。 第二接地部分布置在第一电力部分的下方。 第二动力部分布置在第一接地部分的下方。 第一功率部分的一部分与第二功率部分的一部分重叠，并且第一接地部分的一部分与第二接地部分的一部分重叠，以在第一层和第二层之间提供零强度电场。 第一功率部分经由第一通孔耦合到第二功率部分。 第一接地部分经由第二通孔耦合到第二接地部分。

公开(公告)号：US20090085691A1

公开(公告)日：2009-04-02

申请号：US12007793

申请日：2008-01-15

Applicant: Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

Inventor： Han Kim ,  Je-Gwang Yoo ,  Mi-Ja Han ,  Dae-Hyun Park

IPC: H03H7/00 ,  H05K3/30

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/0236 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09663 ,  H05K2201/10636 ,  H05K2201/10643 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: A printed circuit board having an embedded chip capacitor is disclosed. According to an embodiment of the present invention, a printed circuit board having an embedded chip capacitor can include a first conductive layer; a second conductive layer, placed away from the first conductive layer; a chip capacitor, placed between the first conductive layer and the second conductive layer and having a second electrode, connected to the second conductive layer; and a via, connecting the first conductive layer to a first electrode of the chip capacitor. With the present invention, a problem mixed signals can be solved in the printed circuit board including an analog circuit and a digital circuit board by using the chip capacitor embedded in the printed circuit board as an electromagnetic bandgap structure. Here, various electrical devices or elements are mounted in the printed circuit board.

Abstract translation: 公开了一种具有嵌入式芯片电容器的印刷电路板。 根据本发明的实施例，具有嵌入式芯片电容器的印刷电路板可以包括第一导电层; 远离所述第一导电层放置的第二导电层; 芯片电容器，放置在第一导电层和第二导电层之间，并具有连接到第二导电层的第二电极; 以及将所述第一导电层连接到所述芯片电容器的第一电极的通孔。 利用本发明，通过使用嵌入在印刷电路板中的片状电容器作为电磁带隙结构，可以在包括模拟电路和数字电路板的印刷电路板中解决问题混合信号。 这里，各种电气设备或元件安装在印刷电路板中。

公开(公告)号：US20090061660A1

公开(公告)日：2009-03-05

申请号：US12230037

申请日：2008-08-22

Applicant: Mitsuru Honjo

Inventor： Mitsuru Honjo

IPC: H05K1/00

CPC classification number: H05K3/363 ,  H05K1/056 ,  H05K2201/055 ,  H05K2201/09663 ,  H05K2203/041

Abstract: The connection structure between wired circuit boards connects a first wired circuit board and a second wired circuit board. The first wired circuit board includes a metal supporting layer, a first insulating layer formed on the metal supporting layer, and a first conductive pattern formed on the first insulating layer and having a first terminal portion. The metal supporting layer is arranged so as not to be opposed to the first terminal portion in a thickness direction. The first terminal portion and the first insulating layer opposed to the first terminal portion in a thickness direction are folded back into a curved shape. The second wired circuit board includes a second insulating layer, and a second conductive pattern formed on the second insulating layer and having a second terminal portion. The first terminal portion and the second terminal portion are electrically connected to each other.

Abstract translation: 布线电路板之间的连接结构连接第一布线电路板和第二布线电路板。 第一布线电路板包括金属支撑层，形成在金属支撑层上的第一绝缘层和形成在第一绝缘层上并具有第一端子部分的第一导电图案。 金属支撑层被布置成在厚度方向上不与第一端子部分相对。 在厚度方向上与第一端子部分相对的第一端子部分和第一绝缘层被折回到弯曲的形状。 第二布线电路板包括第二绝缘层和形成在第二绝缘层上并具有第二端子部分的第二导电图案。 第一端子部分和第二端子部分彼此电连接。

公开(公告)号：US07463273B2

公开(公告)日：2008-12-09

申请号：US11489514

申请日：2006-07-20

Applicant: Norito Tsujimoto

Inventor： Norito Tsujimoto

IPC: B41J2/32

CPC classification number: G01K1/20 ,  B41J2/32 ,  B41J2/345 ,  B41J29/02 ,  B41J29/38 ,  G01K1/14 ,  H05K1/0201 ,  H05K2201/062 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09727 ,  H05K2201/10151

Abstract: A printer capable of correctly sensing the internal ambient temperature of a printer body with no influence by an electronic component such as a power supply component reaching a high temperature is obtained. This printer comprises a temperature sensor chip for sensing the internal ambient temperature of the printer body, the electronic component and a ground pattern formed on a wiring board for grounding the temperature sensor chip and the electronic component. A portion of the ground pattern connected to the temperature sensor chip is partially formed narrower than another portion of the ground pattern connected to the electronic component.

Abstract translation: 获得能够正确地感测打印机主体的内部环境温度的打印机，其不受诸如达到高温的电源部件之类的电子部件的影响。 该打印机包括用于感测打印机主体的内部环境温度的温度传感器芯片，电子部件和形成在用于使温度传感器芯片和电子部件接地的布线板上的接地图案。 连接到温度传感器芯片的接地图案的一部分部分地形成为比连接到电子部件的接地图案的另一部分更窄。

公开(公告)号：US20080266026A1

公开(公告)日：2008-10-30

申请号：US12010558

申请日：2008-01-25

Applicant: Mi-Ja Han ,  Han Kim ,  Dae-Hyun Park ,  Jae-Joon Lee

Inventor： Mi-Ja Han ,  Han Kim ,  Dae-Hyun Park ,  Jae-Joon Lee

IPC: H03H7/00

CPC classification number: H01P1/2005 ,  H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/0969

Abstract: An electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. In accordance with an embodiment of the present invention, the electromagnetic bandgap structure can include a first metal layer; a first dielectric layer, stacked in the first metal layer; a metal plate, stacked in the first dielectric layer; a via, connecting the first metal layer to the metal plate; a second dielectric layer, stacked in the metal plate and the first dielectric layer; and a second metal layer, stacked in the second dielectric layer. Here, a hole can be formed on the metal plate. With the present invention, the electromagnetic bandgap structure can lower a noise level more within the same frequency band as compared with other structures having the same size.

Abstract translation: 公开了可解决模拟电路和数字电路之间的混合信号问题的电磁带隙结构和印刷电路板。 根据本发明的实施例，电磁带隙结构可以包括第一金属层; 第一介电层，堆叠在第一金属层中; 金属板，堆叠在第一介电层中; 通孔，将所述第一金属层连接到所述金属板; 第二电介质层，堆叠在所述金属板和所述第一介电层中; 和第二金属层，堆叠在第二介电层中。 这里，可以在金属板上形成孔。 利用本发明，与具有相同尺寸的其他结构相比，电磁带隙结构可以在相同频带内更低噪声水平。

公开(公告)号：US20080257592A1

公开(公告)日：2008-10-23

申请号：US12145502

申请日：2008-06-25

Applicant: Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

Inventor： Hubert Harrer ,  Andreas Huber ,  Thomas-Michael Winkel

IPC: H05K7/06

CPC classification number: H05K1/0265 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/10189 ,  Y10T29/49156

Abstract: An apparatus for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots are introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.

Abstract translation: 用于平衡印刷电路板（PWB）中的电源平面引脚电流的装置提供了减少电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。 在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。 连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。 槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。 所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

公开(公告)号：US20080216298A1

公开(公告)日：2008-09-11

申请号：US12045656

申请日：2008-03-10

Applicant: George Dudnikov

Inventor： George Dudnikov

IPC: H01G4/30 ,  H05K3/20

CPC classification number: H05K1/162 ,  H01G4/06 ,  H01G4/30 ,  H01G4/306 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/113 ,  H05K1/18 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/0191 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0355 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09518 ,  H05K2201/09663 ,  H05K2203/162 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49036 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155

Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.

Abstract translation: 提供了一种用于制造嵌入式电容堆叠的新方法和一种新颖的电容堆叠装置，其具有用作结构衬底的电容性芯，其上可以添加交替的薄导电箔和纳米粉末负载的电介质层并进行可靠性测试。 这种分层和测试允许电容堆叠的薄介电层的早期故障检测。 电容堆叠可以被配置为提供多个隔离的电容元件，其向一个或多个电气元件提供隔离的，器件特定的去耦电容。 电容堆叠可以用作核心衬底，多层电路板的多个附加信号层可以耦合在其上。