公开(公告)号：US20160179135A1

公开(公告)日：2016-06-23

申请号：US14834162

申请日：2015-08-24

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Kengo KUMAGAI

IPC: G06F1/16 ,  G06F1/18 ,  H05K1/18

CPC classification number: G06F1/1613 ,  G06F1/183 ,  H05K1/0243 ,  H05K1/142 ,  H05K1/181 ,  H05K3/403 ,  H05K2201/0397 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/10159

Abstract: An electronic apparatus includes a housing, a first circuit board including a first engaging portion configured to fix the first circuit board to the housing, and a first terminal, and a second circuit board including a second engaging portion configured to fix the second circuit board to the housing, and a second terminal electrically connected to the first terminal.

Abstract translation: 一种电子设备，包括壳体，第一电路板，包括被配置为将第一电路板固定到壳体的第一接合部分和第一端子，以及第二电路板，包括被配置为将第二电路板固定到 壳体和电连接到第一端子的第二端子。

公开(公告)号：US20160148669A1

公开(公告)日：2016-05-26

申请号：US14590163

申请日：2015-01-06

Applicant: HONG FU JIN PRECISION INDUSTRY (WuHan) CO., LTD. ,  HON HAI PRECISION INDUSTRY CO., LTD

Inventor： YONG-ZHAO HUANG ,  YI-HUNG PENG

IPC: G11C11/4074 ,  H05K1/18 ,  H05K1/14

CPC classification number: G11C11/4074 ,  G11C5/04 ,  H05K1/141 ,  H05K2201/10159

Abstract: A motherboard includes a first memory, a power supply, a jumper, a second memory slot and a conversion board. A first idle pin of the second memory slot is coupled to the power supply through the jumper. The motherboard supplies power to the first memory and ensures communication with the first memory by virtue of the conversion board. A conversion board is also provided.

Abstract translation: 主板包括第一存储器，电源，跳线，第二存储器插槽和转换板。 第二存储器插槽的第一空闲引脚通过跳线耦合到电源。 主板为第一个存储器供电，并通过转换板确保与第一个存储器的通信。 还提供了转换板。

公开(公告)号：US20160113115A1

公开(公告)日：2016-04-21

申请号：US14793384

申请日：2015-07-07

Applicant: HEUNG KYU KWON ,  KYOUNG MOOK LIM

Inventor： HEUNG KYU KWON ,  KYOUNG MOOK LIM

IPC: H05K1/18 ,  G06F1/16 ,  H05K1/02 ,  G01R31/28 ,  H05K5/00 ,  H05K1/11

CPC classification number: H05K1/181 ,  G01R31/2884 ,  G06F1/1613 ,  G06F1/1637 ,  H01L23/3121 ,  H01L23/552 ,  H01L25/065 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06517 ,  H01L2225/06596 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15313 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3025 ,  H05K1/0215 ,  H05K1/0268 ,  H05K1/112 ,  H05K2201/10159 ,  H05K2201/10371 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A system on package SoP module includes a printed circuit board (PCB) having a first side and an opposing second side, a first IC attached to the first side, a second IC attached to the second side. The PCB also provides electrical paths for connecting the first IC and the second IC. Conductors by which the second IC is attached to the PCB also allow for electrical testing of the first IC when the SoP is in a system level state.

Abstract translation: 封装SoP模块的系统包括具有第一侧和相对的第二侧的印刷电路板（PCB），附接到第一侧的第一IC，附接到第二侧的第二IC。 PCB还提供用于连接第一IC和第二IC的电气路径。 当SoP处于系统级状态时，第二个IC连接到PCB的导体也允许第一个IC的电气测试。

公开(公告)号：US09318156B2

公开(公告)日：2016-04-19

申请号：US14016235

申请日：2013-09-03

Applicant: Ruban Kanapathippillai ,  Kenneth Alan Okin

Inventor： Ruban Kanapathippillai ,  Kenneth Alan Okin

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  G11C5/04 ,  G11C5/14 ,  G11C16/08 ,  H05K1/18

CPC classification number: G11C16/30 ,  G11C5/04 ,  G11C5/14 ,  G11C16/08 ,  H01R12/725 ,  H05K1/0286 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10212 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/49169

Abstract: In one implementation, flash memory chips are provided with an operating power supply voltage to substantially match a power supply voltage expected at an edge connector of a dual inline memory module. The one or more of the flash memory chips and a memory support application integrated circuit (ASIC) may be mounted together into a multi-chip package for integrated circuits. The one or more flash memory chips and the memory support ASIC may be electrically coupled together by routing one or more conductors between each in the multi-chip package. The multi-chip package may be mounted onto a printed circuit board (PCB) of a flash memory DIMM to reduce the number of packages mounted thereto and reduce the height of the flash memory DIMM. The number of printed circuit board layers may also be reduced, such as by integrating address functions into the memory support ASIC.

Abstract translation: 在一个实施方案中，闪存芯片被提供有工作电源电压以基本上匹配预期在双列直插存储器模块的边缘连接器处的电源电压。 一个或多个闪速存储器芯片和存储器支持应用集成电路（ASIC）可以一起安装到用于集成电路的多芯片封装中。 一个或多个闪存芯片和存储器支持ASIC可以通过在多芯片封装中的每一个之间布线一个或多个导体来电耦合在一起。 多芯片封装可以安装在闪存DIMM的印刷电路板（PCB）上，以减少安装在其上的封装件的数量并降低闪存DIMM的高度。 印刷电路板层的数量也可以减少，例如通过将地址功能集成到存储器支持ASIC中。

公开(公告)号：US20160095246A1

公开(公告)日：2016-03-31

申请号：US14502717

申请日：2014-09-30

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Shawn Noland ,  Daniel Milligan

IPC: H05K7/14 ,  H05K3/30 ,  H05K1/18

CPC classification number: H05K7/1489 ,  H05K1/181 ,  H05K3/301 ,  H05K2201/10159 ,  H05K2201/10507

Abstract: An apparatus as associated method contemplating a housing and a midplane supported by the housing having a midplane connector. A printed circuit board (PCB) having a PCB connector is selectively connectable to the midplane connector. A plurality of data storage devices are arranged on the printed circuit board in a staggered pattern, each electrically connected to the PCB connector via a respective electrical trace in the PCB.

Abstract translation: 一种设备作为相关方法，考虑由具有中平面连接器的壳体支撑的壳体和中平面。 具有PCB连接器的印刷电路板（PCB）可选择性地连接到中面板连接器。 多个数据存储装置以交错图案布置在印刷电路板上，每个电路板经由PCB中的相应电迹线与PCB连接器电连接。

公开(公告)号：US09293444B2

公开(公告)日：2016-03-22

申请号：US14837576

申请日：2015-08-27

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/12 ,  H01L23/50

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/50 ,  H01L24/06 ,  H01L24/09 ,  H01L2224/023 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/09151 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/14361 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0248 ,  H05K1/112 ,  H05K1/181 ,  H05K3/3415 ,  H05K2201/10159 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements.

公开(公告)号：US20160057851A1

公开(公告)日：2016-02-25

申请号：US14464279

申请日：2014-08-20

Applicant: Intel Corporation

Inventor： Shaowu Huang ,  Kai Xiao ,  Beom-Taek Lee ,  Boping Wu ,  Xiaoning Ye

IPC: H05K1/02 ,  H01P3/08 ,  H01P11/00 ,  H05K1/09 ,  H05K3/30 ,  H05K1/18 ,  G06F1/16

CPC classification number: H05K1/023 ,  G06F1/16 ,  H01P1/268 ,  H01P3/08 ,  H01P5/16 ,  H01P11/003 ,  H01R12/737 ,  H01R13/6461 ,  H04L25/03006 ,  H05K1/0216 ,  H05K1/0231 ,  H05K1/0243 ,  H05K1/0246 ,  H05K1/0268 ,  H05K1/09 ,  H05K1/181 ,  H05K3/22 ,  H05K3/303 ,  H05K3/4007 ,  H05K2201/10159 ,  H05K2201/10204

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for electrical signal absorption in an interconnect disposed in a printed circuit board (PCB) assembly. In one instance, a PCB assembly may comprise a substrate, and an interconnect formed in the substrate to route an electrical signal within the PCB. The interconnect may be coupled with a connecting component that is disposed on a surface of the PCB. An absorbing material may be disposed on the PCB to be in direct contact with at least a portion of the connecting component to at least partially absorb a portion of the electrical signal. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及布置在印刷电路板（PCB）组件中的互连件中的电信号吸收的技术和配置。 在一种情况下，PCB组件可以包括衬底和形成在衬底中以在PCB内布置电信号的互连。 互连可以与布置在PCB的表面上的连接部件耦合。 吸收材料可以设置在PCB上以与连接部件的至少一部分直接接触，以至少部分地吸收电信号的一部分。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09252528B2

公开(公告)日：2016-02-02

申请号：US13933288

申请日：2013-07-02

Applicant: GERMANE SYSTEMS, LC

Inventor： Michael Stock ,  Scott Semmler

IPC: H01R13/533 ,  H05K3/00 ,  H05K7/14 ,  H05K1/14 ,  H01R12/70 ,  H05K3/36

CPC classification number: H01R13/533 ,  H01R12/7029 ,  H05K1/141 ,  H05K3/00 ,  H05K3/366 ,  H05K7/1405 ,  H05K2201/09045 ,  H05K2201/09909 ,  H05K2201/10159 ,  H05K2201/10325 ,  H05K2201/10606 ,  Y10T29/49117 ,  Y10T156/1089

Abstract: A circuit board that is to be mounted in a connector socket includes a plurality of electrical connectors located along a side edge of the circuit board. Retention bosses are formed on first and second opposite sides of the circuit board, each of the retention bosses protruding from a surface of the circuit board and extending parallel to and adjacent to the first edge of the circuit board. When the first edge of the circuit board is inserted into a slot of a connector socket, contact surfaces of the first and second retention bosses contact top surfaces of the connector socket to help immobilize the circuit board with respect to the connector socket. Adhesive layers on the contact surfaces of the first and second retention bosses may adhere to the top surfaces of the connector socket to help hold the circuit board immobile with respect to the connector socket.

Abstract translation: 要安装在连接器插座中的电路板包括沿着电路板的侧边缘定位的多个电连接器。 保持凸起形成在电路板的第一和第二相对侧上，每个保持凸起从电路板的表面突出并且平行于并邻近电路板的第一边缘延伸。 当电路板的第一边缘插入连接器插座的插槽中时，第一和第二保持凸台的接触表面接触连接器插座的顶部表面，以帮助固定电路板相对于连接器插座。 第一和第二保持凸起的接触表面上的粘合层可以粘附到连接器插座的顶表面，以帮助保持电路板相对于连接器插座不动。

公开(公告)号：US20160021745A1

公开(公告)日：2016-01-21

申请号：US14800751

申请日：2015-07-16

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： TING-YING WU ,  CHENG-LIN WU ,  CHIN-YUAN LO ,  WEN-SHAN WANG

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0215 ,  H05K1/0289 ,  H05K2201/10159 ,  H05K2201/10704 ,  H05K2201/10712 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00

Abstract: A Ball Grid Array (BGA) formed on printed circuit board is provided. The BGA comprises a first solder ball module and a second solder ball module. The first solder ball module comprises a plurality of first solder balls, wherein one of the first solder balls is grounded for shielding two other first solder balls, and one of the first solder balls is floating. The second solder ball module comprises a plurality of second solder balls, wherein two of the second solder balls are grounded and one of the two grounded second solder balls penetrates the printed circuit board through a plated through hole formed on the printed circuit board for shielding two first solder balls among the first solder balls.

Abstract translation: 提供了一种形成在印刷电路板上的球栅阵列（BGA）。 BGA包括第一焊球模块和第二焊球模块。 第一焊球模块包括多个第一焊球，其中第一焊球之一接地以屏蔽两个其它第一焊球，并且第一焊球中的一个浮动。 第二焊球模块包括多个第二焊球，其中两个第二焊球接地，并且两个接地的第二焊球中的一个通过形成在印刷电路板上的电镀通孔穿透印刷电路板，用于屏蔽两个 第一焊球之间的第一焊球。

公开(公告)号：US20150371698A1

公开(公告)日：2015-12-24

申请号：US14736003

申请日：2015-06-10

Applicant: CANON KABUSHIKI KAISHA

Inventor： Hiroyuki Mizuno

IPC: G11C11/401

CPC classification number: H05K1/0243 ,  G06F13/16 ,  H04L25/02 ,  H05K1/025 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/09781 ,  H05K2201/10159 ,  H05K2203/1572

Abstract: A motherboard includes a main wiring as a transmission line for a signal transmitted by a memory controller, and a branching wiring branched from a branching point of the main wiring and connected to the memory device. Furthermore, the motherboard includes a branching wiring including a land to which a memory device may be joined and branched from a branching point, and an open stub formed extending from the land. According to such a structure, ringing in the waveform of a signal received by the receiving circuit may be suppressed at the time of both single-side mounting and double-side mounting, and also, ringing of a signal may be sufficiently suppressed in the case where the number of DIMMs used by the same substrate is changed.

Abstract translation: 主板包括作为用于由存储器控制器发送的信号的传输线的主配线和从主配线的分支点分支并连接到存储装置的分支布线。 此外，母板包括分支布线，其包括可以从分支点连接并分支的存储器件的焊盘和从焊盘延伸形成的开口短路。 根据这样的结构，在单侧安装和双面安装时可以抑制由接收电路接收的信号的波形的振铃，并且在这种情况下可以充分抑制信号的振铃 其中同一基板使用的DIMM数量发生变化。