公开(公告)号：JP2004342099A

公开(公告)日：2004-12-02

申请号：JP2004128883

申请日：2004-04-23

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： SLEGEL TIMOTHY J ,  BARTIK JANE H ,  HELLER LISA C ,  PFEFFER ERWIN F ,  GAERTNER UTE

IPC: G06F12/08 ,  G06F9/00 ,  G06F9/46 ,  G06F12/10 ,  G06F12/14

CPC classification number: G06F12/1475 ,  G06F12/1036

Abstract: PROBLEM TO BE SOLVED: To filter out a processing restriction in a computing environment in a certain situation to block it to continue a process even if the constraint is satisfied. SOLUTION: One restriction includes a direction for prohibiting a fetch of a storage key in response to a buffer mistake. A processing unit in the computing environment executes comparison of addresses showing whether the fetch can be continued or not when the constraint is satisfied. When the fetch can be continued, the restriction is ignored. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2008016033A

公开(公告)日：2008-01-24

申请号：JP2007176456

申请日：2007-07-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WAGAR BRUCE ,  PFEFFER ERWIN F ,  GAERTNER UTE

IPC: G06F12/08

CPC classification number: G06F12/0897 ,  G06F12/0804

Abstract: PROBLEM TO BE SOLVED: To provide a buffered indexing used for a cache to synchronize parent entries with child entries.
SOLUTION: A method for synchronization uses linking of multiple entries in lower-level tables to single entries in a higher-level table with a buffered index value. This index value increments each time the higher-level entry is replaced or invalidated. Multiple sets of index values are maintained, so that when one set is exhausted, processing can continue with one of other sets. All corresponding lower-level entries with index values from the old (dirty) set can then be scrubbed while new entries are built from the new (clean) set. Scrubbing can take place in the background, and can be suspended and resumed at any time so as to not impact request service times of the tables.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供用于缓存的缓冲索引，以使父条目与子条目同步。 解决方案：同步方法使用下级表中的多个条目与具有缓冲索引值的上级表中的单个条目进行链接。 每次上级条目被替换或无效时，该索引值将递增。 维持多组索引值，以便当一组耗尽时，处理可以继续其他集合之一。 然后，可以从新的（干净的）集合构建新的条目，然后可以擦除所有相应的较低级别的条目，其中旧的（脏）集合的索引值。 擦洗可以在后台进行，可以随时暂停和恢复，以免影响表的请求服务时间。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2002358235A

公开(公告)日：2002-12-13

申请号：JP2002115333

申请日：2002-04-17

Applicant: IBM

Inventor： GAERTNER UTE ,  HAGSPIEL NORBERT ,  LEHNERT FRANK ,  PFEFFER ERWIN ,  SCHELM KERSTIN

IPC: G06F12/1027 ,  G06F12/08 ,  G06F12/10

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system of sharing a TLB2 among CPUs transparently in the CPU architecture and therefore in compliance with the architecture rule. SOLUTION: This invention, in general, refers to a shared memory multiprocessor system of IBM ESA/390 or RS/6000 system, or the like, and in particular refers to the method and the system that share, among a plurality of CPUs, the translation lookaside buffer(TLB2) of second level to improve the performance and reduce a chip area necessary for buffering the result of virtual/absolute address translation. The invented TLB2 configuration includes a plurality of small arrays dedicated for a specific CPU, thus providing an interface for a main array shared among CPUs. The dedicated array is required to meet systematic restrictions and provide a link to a shared array commonly used by a plurality of CPUs.

公开(公告)号：GB2496328A

公开(公告)日：2013-05-08

申请号：GB201300337

申请日：2011-05-19

Applicant: IBM

Inventor： KOEHLER THOMAS ,  GAERTNER UTE

IPC: G06F12/10 ,  G06F12/0855 ,  G06F12/1027

Abstract: An improved method for address translation in a system with a address translation unit (1) containing a translation engine (26) configured to perform a translation table fetch and a translation look aside buffer (28) configured to perform a lookup operation for fast address translation,is disclosed. The method comprises performing the lookup operation in the translation look aside buffer (28) based on a first translation request as current translation request, wherein a respective absolute address is returned to a corresponding requestor (LSU, COP, IFU) for the first translation request as translation result in case of a hit; activating the translation engine (26) to perform at least one translation table fetch in case the current translation request does not hit an entry in the translation look aside buffer (28);wherein the translation engine (26) is idle waiting for the at least one translation table fetch to return data, reporting the idle state of the translation engine (26) as lookup under miss condition and accepting a currently pending translation request as second translation request, wherein a lookup under miss sequence is performed in the translation look aside buffer (28) based on said second translation request.

公开(公告)号：DE69831282T2

公开(公告)日：2006-08-10

申请号：DE69831282

申请日：1998-02-05

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS JOERG DIPL ING ,  KOEHLER THOMAS DIPL ING ,  PFEFFER ERWIN DIPL ING

IPC: G06F9/38 ,  G06F9/30

Abstract: The invention relates to the area of register renaming and allocation in superscalar computer systems. When a multitude of instructions in the instruction stream reads from or writes to a certain logical register, said logical register will have to be represented by a multitude of physical registers. Therefore, there have to exist several physical rename registers per logical register. The oldest one of said rename registers defines the architected state of the computer system, the in-order state. The invention provides a method for administration of the various register instances. Both the registers representing the in-order state and the various rename instances are kept in one common circular buffer. There exist two pointers per logical register: The first one, the in-order pointer, points to the register that represents the in-order state, the second one, the rename pointer, points to the most recent rename instance.

公开(公告)号：BR112023021648A2

公开(公告)日：2023-12-26

申请号：BR112023021648

申请日：2022-05-31

Applicant: IBM

Inventor： GIAMEI BRUCE ,  BORNTRAEGER CHRISTIAN ,  YOST CHRISTINE ,  OSISEK DAMIAN ,  TZORTZATOS ELPIDA ,  HELLER LISA ,  SLEGEL TIMOTHY ,  GAERTNER UTE

IPC: G06F12/14 ,  G06F12/1009 ,  G06F12/1027

Abstract: instrução de redefinição de proteção de tradução de endereço dinâmico. uma instrução é fornecida para executar uma operação de redefinição de proteção de tradução de endereço quando executada. a execução da instrução inclui determinar, por um processador, que um bit de proteção de tradução de endereço em uma entrada de tabela de tradução especificada associada a um bloco de armazenamento deve ser redefinido. com base na determinação de que o bit de proteção de tradução de endereço deve ser redefinido, a execução da instrução inclui a redefinição do bit de proteção de tradução de endereço para desativar a proteção contra gravação para o bloco de armazenamento. a redefinição está ausente, aguardando uma ação de um ou mais outros processadores do ambiente de computação.

公开(公告)号：DE112011100982B4

公开(公告)日：2018-09-06

申请号：DE112011100982

申请日：2011-05-19

Applicant: IBM

Inventor： KOEHLER THOMAS ,  GAERTNER UTE

IPC: G06F12/10 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/1027

Abstract: Adressumsetzungseinheit zur zur Bearbeitung von priorisierten Anforderungen, aufweisendeine Umsetzungseinrichtung (26), die so konfiguriert ist, dass sie einen Umsetzungstabellenabruf ausführt, undeinen Adressumsetzpuffer (28), der so konfiguriert ist, dass er einen Suchvorgang zur schnellen Adressumsetzung ausführt,wobei der Adressumsetzpuffer (28) einen Suchvorgang zu einer ersten Umsetzungsanforderung mit höchster Priorität als aktueller Umsetzungsanforderung ausführt und im Falle eines Treffers eine entsprechende absolute Adresse als Umsetzungsergebnis für die erste Umsetzungsanforderung an einen entsprechenden Anforderer (LSU, COP, IFU) rücküberträgt;wobei die Umsetzungseinrichtung (26) mindestens einen Umsetzungstabellen-Abrufvorgang ausführt, falls die aktuelle Umsetzungsanforderung keinen Eintrag im Adressumsetzpuffer (28) als Treffer liefert;wobei die Umsetzungseinrichtung (26) in inaktivem Zustand auf die Rückübertragung von Daten aus dem mindestens einen Umsetzungstabellen-Abrufvorgang wartet und den inaktiven Zustand als Bedingung „Suche bei Fehlschlag“ meldet; undwobei eine von mehreren Umsetzungsanforderungen mit aktuell höchster Priorität als zweite Umsetzungsanforderung im gemeldeten Zustand „Suche bei Fehlschlag“ von der Adressumsetzungseinheit sofort angenommen wird und im Adressumsetzpuffer (28) für die zweite Umsetzungsanforderung nach einem Treffer gesucht wird,wobei die die Adressumsetzungseinheit ausgebildet ist, eine Vielzahl von anstehenden Umsetzungsanforderungen als zweite Umsetzungsanforderung zu speichern, um eine Verarbeitungsreihenfolge und/oder eine Reihenfolge der Rückübertragung von Ergebnissen der mehr als einen zweiten Umsetzungsanforderung mit einer Prioritätslogik zu verwalten,wobei als zweite Umsetzungsanforderung der zweiten gespeicherten Umsetzungsanforderungen, diejenige mit der höchsten Priorität behandelt wird, sobald die aktuelle Anforderung abgeschlossen ist.

公开(公告)号：DE19929051C2

公开(公告)日：2001-10-04

申请号：DE19929051

申请日：1999-06-25

Applicant: IBM

Inventor： GAERTNER UTE ,  GETZLAFF KLAUS J ,  LAUB OLIVER ,  PFEFFER ERWIN

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/38 ,  G06F9/32 ,  G06F9/318

Abstract: A method and system for renaming registers of said system is proposed in which mixed instruction sets, e.g. 32 bit and 64 bit instructions are carried out concurrently in one program. In case of an instruction sequence of a preceding 64 bit instruction and one or more 32 bit instructions to be executed in-order after the 64 bit instruction and where the 32 bit instructions having a data dependence to the preceding 64 bit instruction, said rest of the register range changed by the preceding 64 bit instruction is copied to the corresponding location in a target register of the succeeding 32 bit instruction, at least if the same logical register is specified by the 32 bit instruction as it was specified by the preceding 64 bit instruction. The copy source is addressed by the register number and hold in a list (28).

公开(公告)号：DE10002120A1

公开(公告)日：2000-11-02

申请号：DE10002120

申请日：2000-01-20

Applicant: IBM

Inventor： GAERTNER UTE ,  PFEFFER ERWIN ,  SCHELM KERSTIN ,  MACDOUGALL JOHN

IPC: G06F12/1027 ,  G06F12/10

Abstract: The buffer storage arrangement has two dividing/partial units (82,84). The first one is a converting buffer (82) for certain higher address converting planes and the second a converting buffer (84) for certain lower address converting planes. The second unit (84) is arranged in such a way that is stores special converting cache (TLB) index address data of the higher unit (82) as a data marker flag in the TLB structure of the lower plane. The first converting buffer (TLB1) is a peak level buffer storage and a second (TLB2) is a second level address converting memory. It is arranged in such a way that it makes available this address data in case of a missing address in the first buffer storage and the second TLB2 is arranged so that it has at least two dividing/partial units (81,82,83,84), and LRU data is provided in both dividing/partial units (81,82,83,84). An Independent claim is also included for A Method for the operation of an address converting buffer arrangement.

公开(公告)号：AU2022287210B2

公开(公告)日：2024-12-12

申请号：AU2022287210

申请日：2022-05-31

Applicant: IBM

Inventor： GIAMEI BRUCE ,  SLEGEL TIMOTHY ,  BORNTRAEGER CHRISTIAN ,  OSISEK DAMIAN ,  HELLER LISA ,  GAERTNER UTE ,  YOST CHRISTINE ,  TZORTZATOS ELPIDA

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F12/14

Abstract: An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.