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    NON-VOLATILE CONTENT ADDRESSABLE MEMORY USING PHASE-CHANGE-MATERIAL MEMORY ELEMENTS
    2.
    发明公开
    NON-VOLATILE CONTENT ADDRESSABLE MEMORY USING PHASE-CHANGE-MATERIAL MEMORY ELEMENTS 审中-公开
    相变材料内容可寻址存储器元件不挥发存储器

    公开(公告)号：EP1908076A4

    公开(公告)日：2009-06-17

    申请号：EP06737703

    申请日：2006-03-09

    Applicant: IBM

    Inventor： HSU LOUIS L C ,  JI BRIAN L ,  LAM CHUNG HON ,  WONG HON-SUM PHILIP

    IPC: G11C11/24

    CPC classification number: G11C13/0004 ,  G11C15/046

    Abstract: A non- volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a source connected to a true bit-read- write-search-line, and a drain connected to another end of the first phase change material element; a second phase change material element, the second phase change material element having one end connected to the match-line; and a second transistor, the second transistor having a gate connected to the word-line, a source connected to a complementary bit- read-write-search-line, and a drain connected to another end of the second phase change material element.

    CHARGE PUMP SYSTEM HAVING MULTIPLE CHARGING RATES AND CORRESPONDING METHOD
    5.
    发明申请
    CHARGE PUMP SYSTEM HAVING MULTIPLE CHARGING RATES AND CORRESPONDING METHOD 审中-公开
    充电泵系统具有多种充电率和相应的方法

    公开(公告)号：WO0133706A9

    公开(公告)日：2002-07-04

    申请号：PCT/US0029820

    申请日：2000-10-26

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： HSU LOUIS L C ,  WEINFURTNER OLIVER ,  WORDEMAN MATTHEW R

    IPC: H02M3/07

    CPC classification number: H02M3/073

    Abstract: A charge pump generator system and method is provided in which on or more charge pumps are operated at multiple charging rates depending upon the level reached by a voltage supply. The system includes a limiter which provides a control signal based upon the level of the voltage supply. The control signal selects the frequency of a multiple frequency oscillator coupled thereto. The selected frequency determines the charge transfer rate of a charge pump used to maintain the voltage supply.

    Abstract translation: 提供了一种电荷泵发电机系统和方法，其中根据电压达到的电平，多个充电速率的多个电荷泵运行。 该系统包括限幅器，其基于电压电平的电平提供控制信号。 控制信号选择与其耦合的多频振荡器的频率。 选定的频率决定了用于维持电压供应的电荷泵的电荷转移速率。

    METHOD FOR PLANARIZING SEMICONDUCTOR DEVICE
    6.
    发明专利
    METHOD FOR PLANARIZING SEMICONDUCTOR DEVICE 失效

    公开(公告)号：JP2002076003A

    公开(公告)日：2002-03-15

    申请号：JP2001171139

    申请日：2001-06-06

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS L C ,  STEPHENS JEREMY K ,  WISE MICHAEL

    IPC: H01L21/76 ,  H01L21/285 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a topography extremely reduced on a semiconductor surface formed by a damascene process. SOLUTION: A diamond or diamond like carbon film is adhered to the surface of a substrate as a polishing stop layer before a metal level pattern is formed. Next, a protective film is adhered on the diamond or diamond like carbon polishing stop layer. The protective film can be used as another polishing stop layer. Both the diamond or diamond like carbon film and the protective film are used as a hard mask so that a pattern is formed in a trench that has metallic features. The protective film protects the diamond or diamond like carbon polishing stop layer during a pattern forming process. After a conductive metal layer is adhered, the substrate is polished, and redundant conducting materials and the topography are removed.

    MEMORY CELL
    7.
    发明专利
    MEMORY CELL 失效

    公开(公告)号：JPH11168190A

    公开(公告)日：1999-06-22

    申请号：JP27728998

    申请日：1998-09-30

    Applicant: SIEMENS AG ,  IBM

    Inventor： MANDELMAN JACK A ,  HSU LOUIS L C ,  ALSMEIER JOHANN ,  TONTI WILLIAM R

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To obtain a small trench capacitor having sufficiently low parasitic leakage. SOLUTION: A transistor, which includes a gate and first and second diffused regions are provided. A trench capacitor in a substrate electrically connects a dielectric color part 168 at the upper-side part of a trench, a diffused region embedded in a substrate surrounding the lower part of the trench capacitor, a transitor and the capacitor. A node diffused region is included on a collar part. A third diffused region 269 is provided in a substrate neighboring the color part. In order to decrease the leakage, an adequate concentration of doping agent for enhancing the threshold voltage of the gate of a parasitic transistor, which is formed of the color part, the embedded diffused region and node diffusion, is provided.

    LATERAL TRANSISTOR AND METHOD OF MAKING SAME
    8.
    发明专利
    LATERAL TRANSISTOR AND METHOD OF MAKING SAME 未知

    公开(公告)号：CA2007412C

    公开(公告)日：1995-01-17

    申请号：CA2007412

    申请日：1990-01-09

    Applicant: IBM

    Inventor： DESILETS BRIAN H ,  HSIEH CHANG-MING ,  HSU LOUIS L C

    IPC: H01L29/73 ,  H01L21/331 ,  H01L21/763 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/732 ,  H01L29/735 ,  H01L21/461

    Abstract: A method of fabricating a lateral transistor is provided, including the steps of: providing a body of semiconductor material including a device region of a first conductivity type; patterning the surface of the device region to define a first transistor region; filling the patterned portion of the device region surrounding the first transistor region with an insulating material to a height generally equal to the surface of with first transistor region; removing portions of the insulating material so as to define a pair of trenches generally bounding opposite sides of the first transistor region; filling the pair of trenches with doped conductive material of opposite conductivity type to the first transistor region; and annealing the semiconductor body whereby to form second and third transistor regions of opposite conductivity type to the first transistor region in the opposing sides of the first transistor region.

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