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    METHOD OF PREVENTING BRIDGING BETWEEN POLYCRYSTALLINE MICRO-SCALE FEATURES
    1.
    发明申请
    METHOD OF PREVENTING BRIDGING BETWEEN POLYCRYSTALLINE MICRO-SCALE FEATURES 审中-公开
    防止多晶微尺度特征之间桥接的方法

    公开(公告)号：WO0173841A2

    公开(公告)日：2001-10-04

    申请号：PCT/EP0102797

    申请日：2001-03-13

    Applicant: IBM ,  IBM DEUTSCHLAND

    Inventor： CLAVENGER LAWRENCE A ,  NAEEM MUNIR D

    IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L21/76892 ,  H01L21/76885 ,  H01L23/528 ,  H01L2924/0002 ,  Y10T428/24777 ,  Y10T428/24917 ,  Y10T428/24975 ,  H01L2924/00

    Abstract: A method of preventing or at least reducing the likelihood of bridging (20) between adjacent micro-scale polycrystalline structures, and particularly to reducing electrical shorting between adjacent metallization lines of a microcircuit. The method generally entails forming a multilayer structure that comprises a polycrystalline layer (12) and at least one constraining layer (14), and then patterning the multilayer structure to yield a first line (16) and a second line (18) that is narrower in width than the first line. The first line has a patterned edge (24) that is spaced apart from a patterned edge (26) of the second line, so that the first and second lines are electrically insulated from each other. One or more features associated with the first line are then formed that prevent bridging between the first and second lines if excessive lateral grain growth subsequently occurs along the patterned edge of the first line.

    Abstract translation: 防止或至少降低在相邻微尺度多晶结构之间桥接（20）的可能性的方法，特别是减少微电路的相邻金属化线之间的电短路的方法。 该方法通常需要形成包括多晶层（12）和至少一个约束层（14）的多层结构，然后构图多层结构以产生更窄的第一线（16）和第二线（18） 宽度比第一行。 第一线具有与第二线的图案化边缘（26）间隔开的图案化边缘（24），使得第一和第二线路彼此电绝缘。 然后形成与第一线相关联的一个或多个特征，如果沿着第一线的图案化边缘发生过多的横向晶粒生长，则防止第一和第二线之间的桥接。

    METHOD OF REDUCING REACTIVE ION ETCHING LAG IN DEEP- TRENCH SILICON ETCHING
    2.
    发明专利
    METHOD OF REDUCING REACTIVE ION ETCHING LAG IN DEEP- TRENCH SILICON ETCHING 失效

    公开(公告)号：JP2002033313A

    公开(公告)日：2002-01-31

    申请号：JP2001161081

    申请日：2001-05-29

    Applicant: IBM

    Inventor： NAEEM MUNIR D ,  MATHAD GANGADHARA S ,  KIM BYEONG YEOL ,  KUDELKA STEPHAN P ,  LEE BRIAN S ,  LI HONG ,  MORALES ELIZABETH ,  PARK YOUNG-JIN ,  RANADE RAJIV M

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a method of minimizing an RIE lag, which occurs during production of a DT in a DRAM having a large aspect ratio. SOLUTION: Using this method, isotropic etching of a wafer can be prevented and hence a passivation film is formed to such a extent as to require to maintain a profile and shape of a DT in the wafer. The RIE process described here provides a partial DT etched in the wafer to attain a prescribed depth. This passivation film is grown to a certain thickness which is not sufficiently thick to block an opening of the deep-trench. In an alternative method, the passivation film is removed by a non-RIE process. The non-RIE process for removing the film may be wet etching using chemicals, such as hydrofluoric acid (buffered or unbuffered) or the like. Alternatively, a vapor phase of hydrofluoric anhydride or the like and/or un-ionized chemicals may be used. By controlling the film thickness, a prescribed depth of a DT for a high aspect ratio structure can be obtained.

    SELF ALIGNED TRENCH AND METHOD OF FORMING THE SAME
    4.
    发明申请
    SELF ALIGNED TRENCH AND METHOD OF FORMING THE SAME 审中-公开
    自定义沟槽和形成它的方法

    公开(公告)号：WO0225730A3

    公开(公告)日：2002-10-24

    申请号：PCT/US0142263

    申请日：2001-09-24

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  DIVAKARUNI RAMACHANDRAN ,  REITH ARMIN M ,  NAEEM MUNIR D

    IPC: H01L21/8242

    CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10891

    Abstract: A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

    Abstract translation: 可以在制造动态随机存取存储器（DRAM）单元中使用形成沟槽的方法。 在一个方面，第一材料（例如，多晶硅）（104）的第一层形成在半导体区域（例如，硅衬底）（100）之上。 第一层被图案化以去除第一材料的一部分。 然后可以沉积第二材料（例如氧化物）（112,120）以填充第一材料被去除的部分。 在去除第一层第一材料的剩余部分之后，可以在半导体区中蚀刻沟槽（122）。 沟槽将基本上与第二材料对齐。

    FORMATION OF COLLAR OXIDE IN TRENCH
    5.
    发明专利
    FORMATION OF COLLAR OXIDE IN TRENCH 失效

    公开(公告)号：JPH11265882A

    公开(公告)日：1999-09-28

    申请号：JP1528999

    申请日：1999-01-25

    Applicant: IBM ,  SIEMENS AG

    Inventor： NAEEM MUNIR D ,  SENDELBACH MATTHEW J ,  WANG TING-HAO

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a collar oxide in the trench of a semiconductor substrate by selectively etching a conformal oxide layer. SOLUTION: In a semiconductor substrate 1 having (1) a trench 100, (2) (i) the filler surface demarcated by filler material for partially filling the trench 100, (ii) the upper surface outside the trench 100, and (iii) part of a sidewall of the trench which is not covered by the filler material, and (3) a conformal oxide layer formed on the upper surface, the sidewall, and the filler surface, (a) the substrate 1 is brought into contact with a mixture of hydrogen-containing fluorocarbon and a source of oxygen under the reactive ion etching conditions, and then (b) the substrate 1 is brought into contact with a mixture of fluorocarbon which does not contain hydrogen and gas for dilution under the reactive ion etching conditions, and the upper surface and the filler surface are selectively overetched while most of the conformal oxide is left over on the sidewall of the trench to form a collar oxide 41.

    SELF ALIGNED TRENCH AND METHOD OF FORMING THE SAME
    7.
    发明申请
    SELF ALIGNED TRENCH AND METHOD OF FORMING THE SAME 审中-公开
    自对准TRENCH及其形成方法

    公开(公告)号：WO0225730A8

    公开(公告)日：2002-12-27

    申请号：PCT/US0142263

    申请日：2001-09-24

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  DIVAKARUNI RAMACHANDRAN ,  REITH ARMIN M ,  NAEEM MUNIR D

    IPC: H01L21/8242

    CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10891

    Abstract: A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

    Abstract translation: 形成沟槽的方法可用于制造动态随机存取存储器（DRAM）单元。 在一个方面，在半导体区域（例如，硅衬底）（100）上形成第一材料（例如，多晶硅）（104）的第一层。 图案化第一层以去除第一材料的部分。 然后可以沉积第二材料（例如氧化物）（112,120）以填充去除第一材料的部分。 在去除第一材料的第一层的剩余部分之后，可以在半导体区域中蚀刻沟槽（122）。 沟槽将基本上对准第二材料。

    METHOD OF REMOVING RIE LAG IN A DEEP TRENCH SILICON ETCHING STEP
    8.
    发明申请
    METHOD OF REMOVING RIE LAG IN A DEEP TRENCH SILICON ETCHING STEP 审中-公开
    在深层氧化硅蚀刻步骤中移除RIE LAG的方法

    公开(公告)号：WO0193323A3

    公开(公告)日：2002-06-27

    申请号：PCT/US0115997

    申请日：2001-05-18

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： NAEEM MUNIR D ,  LEE BRIAN S ,  MATHAD GANGADHARA S ,  LEE HEON ,  KIM BYEONG YEOL ,  MORALES ELIZABETH ,  KUDELKA STEPHAN P ,  RANADE RAJIV ,  PARK YOUNG-JIN

    IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/311 ,  H01L21/8239

    CPC classification number: H01L21/3081 ,  H01L21/3065

    Abstract: A method of minimizing RIE lag (i.e., the neutral and ion fluxes at the bottom of a deep trench (DT) created during the construction of the trench opening using a side wall film deposition)) in DRAMs having a large aspect ratio (i.e., > 30:1) is described. The method forms a passivation film to the extent necessary for preventing isotropic etching of the substrate, hence maintaining the required profile and the shape of the DT within the substrate. The RIE process described provides a partial DT etched into a substrate to achieve the predetermined depth. The passivation film is allowed to grow to a certain thickness still below the extent that it would close the opening of the deep trench. Alternatively, the passivation film is removed by a non-RIE etching process. The non-RIE process that removes the film can be wet etched with chemicals, such as hydrofluoric acid (buffered or non buffered) or, alternatively, using vapor phase and/or non-ionized chemicals, such as anhydrous hydrofluoric acid. The controlled thickness of the film allows achieving a predetermined DT depth for high aspect ratio structures

    Abstract translation: 最小化RIE滞后的方法（即，在使用侧壁膜沉积的沟槽开口的构造期间产生的深沟槽（DT）的底部处的中性和离子通量））具有大纵横比的DRAM（即， > 30：1）。 该方法形成钝化膜，以防止基板的各向同性蚀刻所必需的程度，从而将所需的轮廓和DT的形状保持在基板内。 所述的RIE工艺提供了蚀刻到衬底中以实现预定深度的部分DT。 允许钝化膜生长到一定厚度，仍然低于其将关闭深沟槽的开口的程度。 或者，通过非RIE蚀刻工艺去除钝化膜。 可以用诸如氢氟酸（缓冲或非缓冲）的化学品或者使用蒸气相和/或非电离化学物质如无水氢氟酸来湿法蚀刻除去膜的非RIE工艺。 膜的受控厚度允许实现高纵横比结构的预定DT深度

    METHOD OF FORMING NANO-SCALE STRUCTURES FROM POLYCRYSTALLINE MATERIALS AND NANO-SCALE STRUCTURES FORMED THEREBY
    9.
    发明专利
    METHOD OF FORMING NANO-SCALE STRUCTURES FROM POLYCRYSTALLINE MATERIALS AND NANO-SCALE STRUCTURES FORMED THEREBY 未知

    公开(公告)号：MY120870A

    公开(公告)日：2005-11-30

    申请号：MYPI20011041

    申请日：2001-03-07

    Applicant: IBM

    Inventor： NAEEM MUNIR D ,  CLEVENGER LAWRENCE A

    IPC: H01L21/28 ,  H01L21/768

    Abstract: A METHOD OF FORMING NANO-SCALE FEATURES WITH CONVENTIONAL MULTILAYER STRUCTURE, AND NANO-SCALE FEATURES FORMED THEREBY. THE METHOD GENERALLY ENTAILS FORMING A MULTILAYER STRUCTURE THAT INCLUDES A POLYCRYSTALLINE LAYER AND AT LEAST ONE CONSTRAINING LAYER. THE MULTILAYER STRUCTURE IS PATTERNED TO FORM FIRST AND SECOND STRUCTURES, EACH OF WHICH INCLUDES THE POLYCRYSTALLINE AND CONSTRAINING LAYERS. AT LEAST THE FIRST STRUCTURE IS THEN LOCALLY HEATED, DURING WHICH TIME THE CONSTRAINING LAYER RESTRICTS THE THERMAL EXPANSION OF THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE. AS A RESULT, STRESSES ARE INDUCED IN THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE. AS A RESULT, STRESSES ARE INDUCED IN THE POLYCRYSTALLINE LAYER OF THE FIRST STRUCTURE, CAUSING SUBSTANTIALLY TWO-DIMENSIONAL GRAIN GROWTH FROM THE EDGE OF THE FIRST STRUCTURE. SUFFICIENT GRAIN GROWTH OCCURS TO PRODUCE A THIRD STRUCTURE WHICH, BASED ON THE GRAIN SIZE OF THE POLYCRYSTALLINE LAYER, WILL BE A NANO-SCALE STRUCTURE. WHEN APPROPRIATELY CONFIGURED, NANO-SCALE STRUCTURES CAN BE FORMED AS OPERATIVE COMPONENTS OF ELECTRICAL, MENCHANICAL, OPTICAL AND FLUID-HANDLING DEVICES.

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