公开(公告)号：EP1470447A4

公开(公告)日：2007-10-10

申请号：EP02784585

申请日：2002-11-25

Applicant: IBM

Inventor： RANKIN JED H ,  SCHNEIDER CRAIN E ,  SMYTH JOHN S ,  WATTS ANDREW J

IPC: G03C5/00 ,  G01D18/00 ,  G03F7/20 ,  G06F17/50 ,  G06F19/00 ,  G21K5/00 ,  H01L21/027

CPC classification number: G03F7/70508 ,  G03F7/70558

Abstract: A method of implementing a new reticle for manufacturing semiconductor devices on a wafer which involves performing measurements (420) on the reticle and assigning an initial exposure dose (470) by using a predetermined algorithm (450). The exposure control system (490) utilizes reticle CD data (430, 440) for automatically calculating reticle exposure offset values, i.e. reticle factors (510). A correlation of reticle size deviations (500) to calculated reticle factors (510) is used to derive a reticle factor (510) for the new reticle. The derived reticle factor (510) is then used to predict (450) an initial exposure condition for the new reticle which is applied (470) to the lithography tool (410) for achieving a wafer design dimension.

公开(公告)号：EP2281303A4

公开(公告)日：2013-11-20

申请号：EP09798429

申请日：2009-06-18

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/334 ,  G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: A design structure is provided for spacer fill structures and, more particularly, spacer fill structures, a method of manufacturing and a design structure for reducing device variation is provided. The structure includes a plurality of dummy fill shapes in different areas of a device which are configured such that gate perimeter to gate area ratio will result in a total perimeter density being uniform across a chip.

公开(公告)号：EP1805795A4

公开(公告)日：2010-10-06

申请号：EP05809789

申请日：2005-10-11

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L27/12 ,  H01L21/336 ,  H01L21/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/04 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

公开(公告)号：EP1690294A4

公开(公告)日：2010-09-22

申请号：EP04810448

申请日：2004-11-05

Applicant: IBM

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/336 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66795

公开(公告)号：EP1581968A4

公开(公告)日：2007-04-18

申请号：EP02808339

申请日：2002-12-20

Applicant: IBM

Inventor： RANKIN JED H ,  ABADEER WAGDI W ,  BROWN JEFFREY S ,  CHATTY KIRAN V ,  TONTI WILLIAM R ,  GAUTHIER ROBERT J JR ,  FRIED DAVID M

IPC: H01L23/525 ,  H01L21/82 ,  H01L21/84 ,  H01L27/06 ,  H01L27/118 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L23/5252 ,  H01L27/0629 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/785 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is described for fabricating and antifuse structure (100) integrated with a semiconductor device such as a FINFET or planar CMOS devise. A region of semiconducting material (11) is provided overlying an insulator (3) disposed on a substrate (10); an etching process exposes a plurality of corners (111-114) in the semiconducting material. The exposed corners are oxidized to form elongated tips (111t-114t) at the corners; the oxide (31) overlying the tips is removed. An oxide layer (51), such as a gate oxide, is then formed on the semiconducting material and overlying the corners; this layer has a reduced thickness at the corners. A layer of conducting material (60) is formed in contact with the oxide layer (51) at the corners, thereby forming a plurality of possible breakdown paths between the semiconducting material and the layer of conducting material through the oxide layer. Applying a voltage, such as a burn-in voltage, to the structure converts at least one of the breakdown paths to a conducting path (103, 280).

公开(公告)号：JP2002198538A

公开(公告)日：2002-07-12

申请号：JP2001319845

申请日：2001-10-17

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  ARNE W BALLANTINE ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate transistor having a relatively thin epitaxial growth channel. SOLUTION: The epitaxial growth channel is formed, and then a damascene gate is formed, thus forming a silicon-on-insulator(SOI) MOSFET of a dual gate. In the dual-gate MOSFET, a narrow channel should be provided, thus increasing a current drive per layout width, and achieving low out conductance.

公开(公告)号：JP2002083887A

公开(公告)日：2002-03-22

申请号：JP2001197828

申请日：2001-06-29

Applicant: IBM

Inventor： CHEN BOMY A ,  HARRINGTON JAY G ,  KEVIN M HALLIHAN ,  DENNIS HOINIAKKU ,  CHAN HON RAMU ,  HYUN KOO LEE ,  REBECCA D MII ,  RANKIN JED H

IPC: H01L21/8247 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for an EEPROM device, having a high performance logic (such as complementary metal-oxide semiconductor(CMOS), for example), or EEPROM device, being integrated with a nonvolatile random access memory(NVRAM). SOLUTION: The EEPROM device is provided with mutually self-matched floating gate and program gate. During programming, electronic tunneling occurs between the floating gate and the program gate.

公开(公告)号：JP2005217418A

公开(公告)日：2005-08-11

申请号：JP2005021176

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L21/762 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L29/66795 ,  H01L29/66803

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a fin-type field-effect transistor (FinFET) having an embedded oxide layer 130 on a substrate 110, at least one-layer first structure 112 on the embedded oxide layer and at least one-layer second fin structure 114 on the embedded oxide layer and a manufacturing method of the same. SOLUTION: A first spacer 120 is adjacent to the fin structure 112, and a second spacer 118 is adjacent to the second fin structure 114. The area that the first spacer covers the first fin structure is wider than the area that the second spacer covers the second fin structure. As long as a fin has a wider spacer, a relatively narrow semiconductor doping area 113 is given, and as long as the fin has a narrower spacer, a relatively broader semiconductor doping area 115 is given. Therefore, a difference in doping between the first fin and the second fin takes place depending upon the spacers of different dimensions. The effective width of the second fin varies with the difference in doping between the first fin and the second fin as compared to the first fin. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供在衬底110上具有嵌入氧化物层130的鳍式场效应晶体管（FinFET）的结构，在嵌入的氧化物层上的至少一层第一结构112和 在嵌入的氧化物层上的至少一层的第二鳍结构体114及其制造方法。 解决方案：第一间隔件120邻近翅片结构112，第二间隔件118与第二翅片结构114相邻。第一间隔件覆盖第一翅片结构的区域比第二间隔件118的区域宽 间隔件覆盖第二鳍结构。 只要翅片具有更宽的间隔物，就给出相对较窄的半导体掺杂区域113，并且只要鳍片具有较窄的间隔物，就给出相对较宽的半导体掺杂区域115。 因此，根据不同尺寸的间隔物，发生第一鳍片和第二鳍片之间的掺杂差异。 与第一鳍片相比，第二鳍片的有效宽度随着第一鳍片和第二鳍片之间的掺杂差异而变化。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：WO2006044349A3

公开(公告)日：2007-06-07

申请号：PCT/US2005036471

申请日：2005-10-11

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/04 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A planar substrate device (100) integrated with fin field effect transistors (FinFETs) and a method of manufâcture comprises a silicon-on-insulator (SOI) wafer (101) comprising a substrate (103); a buried insulator layer (105) over the substrate (103); and a semiconductor layer (115) over the buried insulator layer (105). The structure (100) further comprises a FinFET (130) over the buried insulator layer (105) and a field effect transistor (FET) (131) integrated in the substrate (103), wherein the FET (127) gate is planar to the FinFET gate (125). The structure (100) further comprises retrograde well regions (104, 106, 108, 110) configured in the substrate (103). In one embodiment, the structure (100) further comprises a shallow trench isolation region (111) configured in the substrate (103).

Abstract translation: 与鳍状场效应晶体管（FinFET）集成的平面基板装置（100）和制造方法包括：包含基板（103）的绝缘体上硅（SOI）晶片（101）; 在所述衬底（103）上方的掩埋绝缘体层（105）; 以及在所述掩埋绝缘体层（105）上方的半导体层（115）。 所述结构（100）还包括在所述掩埋绝缘体层（105）上的FinFET（130）和集成在所述衬底（103）中的场效应晶体管（FET）（131），其中所述FET（127）栅极与 FinFET门（125）。 结构（100）还包括配置在基底（103）中的逆行井区（104,106,108,110）。 在一个实施例中，结构（100）还包括构造在衬底（103）中的浅沟槽隔离区（111）。

公开(公告)号：WO2006044349A9

公开(公告)日：2007-08-16

申请号：PCT/US2005036471

申请日：2005-10-11

Applicant: IBM ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

Inventor： ANDERSON BRENT A ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/04 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795

Abstract: A planar substrate device (100) integrated with fin field effect transistors (FinFETs) and a method of manufâcture comprises a silicon-on-insulator (SOI) wafer (101) comprising a substrate (103); a buried insulator layer (105) over the substrate (103); and a semiconductor layer (115) over the buried insulator layer (105). The structure (100) further comprises a FinFET (130) over the buried insulator layer (105) and a field effect transistor (FET) (131) integrated in the substrate (103), wherein the FET (127) gate is planar to the FinFET gate (125). The structure (100) further comprises retrograde well regions (104, 106, 108, 110) configured in the substrate (103). In one embodiment, the structure (100) further comprises a shallow trench isolation region (111) configured in the substrate (103).

Abstract translation: 与鳍式场效应晶体管（FinFET）集成的平面衬底器件（100）和制造方法包括：包括衬底（103）的绝缘体上硅（SOI）晶片（101）; 衬底（103）之上的掩埋绝缘体层（105）; 和在掩埋绝缘体层（105）上的半导体层（115）。 所述结构（100）还包括在所述掩埋绝缘体层（105）之上的FinFET（130）和集成在所述衬底（103）中的场效应晶体管（FET）（131），其中所述FET（127）栅极与所述 FinFET栅极（125）。 结构（100）还包括配置在衬底（103）中的逆行阱区（104,106,108,110）。 在一个实施例中，结构（100）还包括配置在衬底（103）中的浅沟槽隔离区（111）。