公开(公告)号：JP2001044390A

公开(公告)日：2001-02-16

申请号：JP2000209997

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRONNER GARY ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain non-planar type transistor structure by arranging an active transistor device partially on the sidewall of a deep trench in a cell, and aligning the side wall to a first crystal plane with a crystal orientation along the single- crystal axis. SOLUTION: A deep trench accumulation capacitor 10 is formed in a pad 22 and a substrate 24, and a pattern is formed on the pad 22 using a light lithography step. Then, using such a dry etching step as reactive ion etching, a trench 20 is formed to a desired depth in the substrate 24 through the pad 22. Then, an active transistor device is partially provided on a sidewall 32 of the trench 20, and the sidewall 32 is aligned to first crystal planes (001) and (011) with a crystal orientation set along the single-crystal axis.

公开(公告)号：JP2001044384A

公开(公告)日：2001-02-16

申请号：JP2000220682

申请日：2000-07-21

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J ,  TOBBEN DIRK

IPC: H01L27/108 ,  H01L21/76 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce a method for forming an embedded plate diffusion region in a deep trench storage capacitor by filling a non-photosensitive underfill material into the lower region of a trench before forming a collar at the upper region of the trench. SOLUTION: A trench 10 is covered with a thin barrier film 30, and a non- photosensitive underfill 16 is filled into the lower region of the trench 10. Then, the barrier film 30 is eliminated by an upper region 223 of the trench 10 by chemical etching using wet solution or the like. Also, the underfill 16 masks a lower region, 24 while the barrier film 30 at the upper region 22 is being removed. Then, the underfill 16 is removed from a lower region by stripping or the like by a chemical containing HF, and a collar 32 is formed at the upper region 22 by thermal oxidation growth or the like by the local oxidation process.

公开(公告)号：JP2001085637A

公开(公告)日：2001-03-30

申请号：JP2000245911

申请日：2000-08-14

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： FURUKAWA TOSHIHARU ,  GRUENING ULRIKE ,  HORAK DAVID V ,  MANDELMAN JACK A ,  RADENS CARL J ,  RUPP THOMAS S

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain a vertical DRAM having a self-aligned word line conductor on the sidewall of a trench by forming a word line conductor having a sidewall aligned with the sidewall of the trench. SOLUTION: A pad nitride is removed selectively depending on the oxide 240 in an STI region 228. A screen oxide is then grown and array region p-well implantation is carried out and an N+ dopant is implanted in order to form a second diffusion region 210. Subsequently, source and drain implantation is carried out in a support region in order to form a diffusion region 288 and an oxide 242 is formed on the sidewalls 219, 233 of a word line conductor 218, 232 and on the sidewall of a support gate. Finally, a bit line conductor 244 of polysilicon is deposited for planarization. Since word line resistance is decreased, a DRAM device having improved performance can be obtained.

公开(公告)号：JP2000277708A

公开(公告)日：2000-10-06

申请号：JP2000073717

申请日：2000-03-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK A ,  NESBIT LARRY ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To prevent resistance of an embedded strap of a DRAM cell from changing by the overlapping manner of a deep trench and an active region. SOLUTION: This semiconductor device contains a semiconductor substrate. At least a pair of deep trenches are formed in the substrate. A collar is formed in at least a part of the sidewall of each of the deep trenches. The inside of each of the deep trenches is filled with a trench filler 44. An embedded strap 46 is formed over the whole of each of the deep trenches and covers the upper surfaces of the trench filler 44 and the collar. An insulating region is formed between a a pair of the deep trenches. A trench upper part dielectric region 52 formed in the deep trench, so as to overlap with the embedded strap 46 of each of the deep trenches.

公开(公告)号：JP2000323684A

公开(公告)日：2000-11-24

申请号：JP2000085406

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： GRUENING ULRIKE ,  HALLE SCOTT ,  RADENS CARL J ,  JEFFREY J WERSER ,  BEINTNER JOCHEN ,  MANDELMAN JACK A ,  WITTMANN JUERGEN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To form a trench capacitor in a semiconductor body. SOLUTION: A trench capacitor 10 and a MOS transistor 9 are provided in a substrate 16 to form a cell 8 of the DRAM, and the cell 8 is separated from adjacent cells by an STI region 28. The capacitor 10 is composed of an insulator 14 enveloping the trench and a first electrode 24 filled with polysilicon 12, is connected to the drain portion 72 through a buried electrode 22, and is insulated from a gate electrode 20 by a dielectric 23. A second electrode 25 is formed in its bottom portion through an insulator 14. A transistor 9 has N-type drain 72 and source 71 in an upper active region 11 of the substrate 16 and operates with a p well as channel.

公开(公告)号：JP2000269464A

公开(公告)日：2000-09-29

申请号：JP2000077068

申请日：2000-03-17

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： PARK YOUNG-JIN ,  RADENS CARL J ,  GERHARD KUNKEL

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To reduce an interference action between a buried strap and an access transistor channel of a semiconductor memory, by making a distance between a gate and the side of a trench larger than the minimum feature size. SOLUTION: A trench 102 forms an angle A at 0 degree to 45 degrees to a word line 104, and the angled portion 108 of an active area 106 forms a herringbone pattern to effectively lay out components such as the trench 102 and a contact 116. A portion 110 of the active area 106 is elongated to a value larger than feature size F to increase an average distance to reduce a dopant interference between the buried strap of the trench 102 and the word line 104. Therefore, this realizes a longer distance between the trench 102 and the bit line contact 116.

公开(公告)号：JP2000353795A

公开(公告)日：2000-12-19

申请号：JP2000139018

申请日：2000-05-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： GRUENING ULRIKE ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/60 ,  H01L21/8242 ,  H01L29/732

Abstract: PROBLEM TO BE SOLVED: To obtain a method of manufacturing an LSI which contains a vertical transistor and is lessened in size, provided at a low cost, and enhanced in reliability. SOLUTION: A capacitor 41 composed of a trench 13, an insulating film 14, and a conductor 16 is formed in a substrate 10, and a stepped part is provided at the upper part of an opening 50 bored in the substrate 10, and then the opening 50 is filled with insulator for the formation of an isolation region 50. The upper part of the stepped part is filled with a conductive material to serve as a strap 904, and N-type ions are implanted for the formation of a source region 61 inside the substrate 10. An insulating film 905 is attached, a gate electrode 108 is deposited, a trench 105 is cut by etching, a spacer 103 is attached, then N-type ions are implanted to form a drain region 106 adjacent to the upper gate 108, and the opening 105 is filled up with conductor to serve as a contact. The strap 904 serves as a source electrode which crosses the capacitor 41 at grade and is electrically connected to the contact 105, which serves as a drain electrode through the intermediary of diffusion regions 61 and 106 located inside the substrate 10.

公开(公告)号：WO02086904A2

公开(公告)日：2002-10-31

申请号：PCT/US0210892

申请日：2002-04-08

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUDELKA STEPHAN P ,  JAIPRAKASH VENKATACHAIAM C ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242 ,  G11C11/00

CPC classification number: H01L27/10864 ,  H01L27/10876 ,  H01L27/10888

Abstract: A method for a memory cell has a trench capacitor and a vertical transistor adjacent to the capacitor. The vertical transistor has a gate conductor above the trench capacitor. The upper portion of the gate conductor is narrower than the lower portion of the gate conductor. The memory cell further includes spacers adjacent the upper portion of the gate conductor and a bitline contact adjacent to the gate conductor. The spacers reduce short circuits between the bitline contact and the gate conductor. The gate contact above the gate conductor has an insulator which separates the gate contact from the bitline. The difference between the width of the upper and lower portions of the gate conductor reduces short circuits between the bitline contact and the gate conductor.

Abstract translation: 存储单元的方法具有沟槽电容器和与电容器相邻的垂直晶体管。 垂直晶体管在沟槽电容器上方具有栅极导体。 栅极导体的上部比栅极导体的下部窄。 存储单元还包括邻近栅极导体的上部的间隔物和邻近栅极导体的位线接触。 间隔物减少了位线接触和栅极导体之间​​的短路。 栅极导体上方的栅极接触具有将栅极接触与位线分离的绝缘体。 栅极导体的上部和下部的宽度之间的差异减小了位线接触和栅极导体之间​​的短路。

公开(公告)号：WO0201567A3

公开(公告)日：2002-02-25

申请号：PCT/US0120221

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10841

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。