公开(公告)号：JP2000277708A

公开(公告)日：2000-10-06

申请号：JP2000073717

申请日：2000-03-16

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  GRUENING ULRIKE ,  KIM BYEONG Y ,  MANDELMAN JACK A ,  NESBIT LARRY ,  RADENS CARL J

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To prevent resistance of an embedded strap of a DRAM cell from changing by the overlapping manner of a deep trench and an active region. SOLUTION: This semiconductor device contains a semiconductor substrate. At least a pair of deep trenches are formed in the substrate. A collar is formed in at least a part of the sidewall of each of the deep trenches. The inside of each of the deep trenches is filled with a trench filler 44. An embedded strap 46 is formed over the whole of each of the deep trenches and covers the upper surfaces of the trench filler 44 and the collar. An insulating region is formed between a a pair of the deep trenches. A trench upper part dielectric region 52 formed in the deep trench, so as to overlap with the embedded strap 46 of each of the deep trenches.

公开(公告)号：JP2001068672A

公开(公告)日：2001-03-16

申请号：JP2000210075

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： DIVAKARUNI RAMA ,  JEFFREY P GANBINO ,  MANDELMAN JACK A ,  RENGARAJAN RAJESH

IPC: H01L21/28 ,  H01L21/265 ,  H01L21/336 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/772 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To obtain an improved structure and a production process of semiconductor device, e.g. MOSFET, in which possibility of thermal shrinkage and permeation of boron are reduced. SOLUTION: A sacrificial oxide layer 1 and a polysilicon/silicon nitride film are deposited sequentially on a substrate 2, an opening is made therein by etching (at the part of 5, 15) and ions are implanted in order to suppress hot carriers 11 thus suppressing punch through 8 between source and drain. After it is filled with a gate insulation film 12, a polysilicon layer 14 and a tungsten layer 15, upper part of an implanted part 18 for extending the source-drain is opened by etching, a spacer 19 is formed therein and contact implantation appropriate to P or N type is carried out. Thereafter, a nitride etch barrier layer 20 is formed, a contact region 21 is opened and filled with a polysilicon layer 22.

公开(公告)号：JP2000228504A

公开(公告)日：2000-08-15

申请号：JP2000028340

申请日：2000-02-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MANDELMAN JACK A ,  LAROSA GIUSEPPE ,  RADENS CARL ,  DIVAKARUNI RAMA ,  GRUENING ULRIKE

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/765 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a dynamic random access memory formed at a semiconductor body comprising individual paired memory cell separated each other by a vertical electric isolation trench and separated from a support circuit. SOLUTION: An isolation trench 20, comprising a side wall, upper part, and lower part, encloses the region of a semiconductor body 10 comprising a memory cell. Thus, the paired memory cell is electrically separated each other, while separated from a support circuit which is not in the enclosed region but contained in the semiconductor body. The isolation trench lower-part is filled with a conductive material 14, which material comprises a side wall part which is at least partially separated from the trench lower-part side wall by a first electric insulator and a lower part electrically connecting to the semiconductor body. The isolation trench upper-part is filled with a second electric insulator.

公开(公告)号：WO0227784A3

公开(公告)日：2003-04-10

申请号：PCT/US0142293

申请日：2001-09-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMA ,  RADENS CARL ,  NESBIT LARRY ,  BERGNER WOLFGANG

IPC: H01L21/8242 ,  H01L23/525

CPC classification number: H01L27/10861 ,  H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A structure and process for semiconductor fuses and antifuses in vertical DRAMS provides fuses and antifuses in trench openings formed within a semiconductor substrate. Vertical transistors may be formed in other of the trench openings formed within the semiconductor substrate. The fuse is formed including a semiconductor plug (108) formed within an upper portion of the trench opening (110) and includes conductive leads (252, 254) contacting the semiconductor plug. The antifuse is formed including a semiconductor plug formed within an upper portion of the trench opening and includes conductive leads formed over the semiconductor plug, at least one conductive lead isolated from the semiconductor plug by an antifuse dielectric. Each of the fuse and antifuse are fabricated using a sequence of process operations also used to simultaneously fabricate vertical transistors according to vertical DRAM technology, the plug forming the gate of the vertical transistor.

Abstract translation: 垂直DRAMS中的半导体熔丝和反熔丝的结构和工艺在半导体衬底内形成的沟槽开口中提供熔丝和反熔丝。 垂直晶体管可以形成在形成在半导体衬底内的其它沟槽开口中。 熔丝形成包括形成在沟槽开口（110）的上部内的半导体插塞（108），并且包括接触半导体插头的导电引线（252,254）。 反熔丝形成包括形成在沟槽开口的上部内的半导体插塞，并且包括形成在半导体插头上的导电引线，至少一个导电引线，其通过反熔丝绝缘体与半导体插塞隔离。 熔丝和反熔丝中的每一个都使用一系列工艺操作来制造，这些工艺操作也用于根据垂直DRAM技术同时制造垂直晶体管，该插头形成垂直晶体管的栅极。

公开(公告)号：WO0247157A3

公开(公告)日：2003-01-30

申请号：PCT/US0144920

申请日：2001-11-29

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DIVAKARUNI RAMA ,  KUDELKA STEPHAN ,  LEE KIL-HO ,  MCSTAY IRENE ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/8242 ,  H01L21/763 ,  H01L21/8234

CPC classification number: H01L27/10867

Abstract: A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the barrier layer. Perform an angled implant into portions of the amorphous silicon masking layer which are not in the shadow of the deep trench. Strip the undoped portions of the amorphous silicon masking layer from the deep trench. Then strip the newly exposed portions of barrier layer exposing a part of the trench fill polysilicon surface and leaving the doped, remainder of the amorphous silicon masking layer exposed. Counterdope the exposed part of the trench fill material. Oxidize exposed portions of the polysilicon trench fill material, and then strip the remainder of the masking layer.

Abstract translation: 用于制造填充有多晶硅沟槽填充材料的单面半导体深沟槽结构的工艺包括以下步骤。 在沟槽填充材料上形成薄膜，氮化硅，阻挡层。 在阻挡层上沉积非晶硅掩模层的薄膜。 对非深度沟槽阴影的非晶硅掩模层的部分进行成角度的注入。 从深沟槽剥离非晶硅掩模层的未掺杂部分。 然后剥离暴露部分沟槽填充多晶硅表面的势垒层的新暴露部分，并且使非晶硅掩模层的掺杂剩余部分露出。 反映出暴露部分的沟槽填充材料。 氧化多晶硅沟槽填充材料的暴露部分，然后剥离掩模层的其余部分。

公开(公告)号：WO0195391A8

公开(公告)日：2002-03-28

申请号：PCT/US0117927

申请日：2001-06-01

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： NESBIT LARRY ,  MCSTAY IRENE LENNOX ,  RADENS CARL ,  TEWS HELMUT HORST ,  DIVAKARUNI RAMA ,  MANDELMAN JACK

IPC: H01L21/8242

CPC classification number: H01L27/10861 ,  H01L27/10867

Abstract: A method of forming relatively thin uniform insulating collar in the storage trench of a storage trench DRAM cell. A DRAM trench is first formed in a silicon substrate. Then, a nitride liner (81) is deposited on the silicon trench walls. The nitride liner may be deposited directly on the silicon walls or on an underlying oxide layer (79). A layer of amorphous silicon (83) is then deposited over the nitride liner. A silicon nitride layer is deposited on the oxidized surface of the amorphous silicon. A resist (83) is formed in the lower portion of the trench, and the exposed silicon nitride layer on top of the amorphous silicon is removed, leaving the upper portion of the amorphous silicon layer exposed. The upper portion of the layer of amorphous silicon is then oxidized so as to form a relatively thin, uniform collar (89) along the entire circumference of the trench. The nitride liner underlying the amorphous silicon layer enhances the thickness uniformity of the amorphous silicon layer and thereby the uniformity of the resulting oxide collar. The nitride liner also acts to limit lateral oxidation of the silicon trench walls during oxidation of the amorphous silicon layer. The nitride liner underlying the collar is also effective in cell operation to control the cell charge at the collar-substrate interface.

Abstract translation: 一种在存储沟槽DRAM单元的存储沟槽中形成相对薄的均匀绝缘环的方法。 首先在硅衬底中形成DRAM沟槽。 然后，氮化物衬垫（81）沉积在硅沟槽壁上。 氮化物衬垫可以直接沉积在硅壁上或下面的氧化物层（79）上。 然后在氮化物衬垫上沉积一层非晶硅（83）。 在非晶硅的氧化表面上沉积氮化硅层。 在沟槽的下部形成抗蚀剂（83），去除非晶硅顶部的露出的氮化硅层，使非晶硅层的上部露出。 然后，非晶硅层的上部被氧化，以便沿沟槽的整个圆周形成相对较薄的均匀的环（89）。 非晶硅层下面的氮化物衬垫增强了非晶硅层的厚度均匀性，从而提高了所得氧化物环的均匀性。 氮化物衬垫还用于在非晶硅层的氧化期间限制硅沟槽壁的横向氧化。 在套环下面的氮化物衬垫在电池操作中也有效地控制在衬套 - 衬底界面处的电池电荷。

公开(公告)号：DE10215666A1

公开(公告)日：2002-11-07

申请号：DE10215666

申请日：2002-04-09

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS ,  MALIK RAIEEV ,  DIVAKARUNI RAMA ,  MANDELMAN JACK A ,  JAIPRAKASH V C

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/8242

Abstract: A structure and method which enables the deposit of a thin nitride liner just before Trench Top Oxide TTO (High Density Plasma) HDP deposition during the formation of a vertical MOSFET DRAM cell device. This liner is subsequently removed after TTO sidewall etch. One function of this liner is to protect the collar oxide from being etched during the TTO oxide sidewall etch and generally provides lateral etch protection which is not realized in the current processing scheme. The process sequence does not rely on previously deposited films for collar protection, and decouples TTO sidewall etch protection from previous processing steps to provide additional process flexibility, such as allowing a thinner strap Cut Mask nitride and greater nitride etching during node nitride removal and buried strap nitrided interface removal. Advantageously, the presence of the nitride liner beneath the TTO reduces possibility of TTO dielectric breakdown between the gate and capacitor node electrode of the vertical MOSFET DRAM cell, while assuring strap diffusion to gate conductor overlap.

公开(公告)号：DE10226568A1

公开(公告)日：2003-02-06

申请号：DE10226568

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MALIK RAJEEB ,  NESBIT LARRY ,  BEINTNER JOCHEN ,  DIVAKARUNI RAMA

IPC: H01L21/762 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：JP2005197749A

公开(公告)日：2005-07-21

申请号：JP2005002025

申请日：2005-01-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEINTNER JOCHEN ,  DIVAKARUNI RAMA ,  JAMMY RAJARAO

IPC: H01L21/8242 ,  H01L21/762 ,  H01L27/108 ,  H01L29/76

CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10894

Abstract: PROBLEM TO BE SOLVED: To provide a structure for a perpendicular-type DRAM capable of being integrated into a process flow, using a flat surface device.
SOLUTION: A method of manufacturing an integrated circuit device comprises steps of etching a trench in a substrate; and forming DRAM cells which include a build-up capacitor 24 at a lower edge and a perpendicular-type MOSFET having a gate conductor 30 covering the build-up capacitor 24 and a boron doped channel. The method further comprises a step of forming a trench adjacent to the DRAM cells and a silicon acid nitriding isolation liner at either side of the DRAM cells. Next, an isolation region is formed in the trench at either side of the DRAM cells. Thereafter, the DRAM cells, including a boron-containing channel region are exposed to a high temperature caused by heat treatment to form a supporting device and so on. A nitride containing isolation liner reduces the isolation of boron in a channel region as compared with an oxide-containing isolation liner essentially without nitrogen.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够使用平面装置集成到工艺流程中的垂直型DRAM的结构。 解决方案：一种制造集成电路器件的方法包括以下步骤：蚀刻衬底中的沟槽; 并且在下边缘处形成包括积聚电容器24的DRAM单元和具有覆盖积层电容器24的栅极导体30和掺杂硼的沟道的垂直型MOSFET。 该方法还包括在DRAM单元的任一侧形成与DRAM单元相邻的沟槽和硅酸氮化隔离衬垫的步骤。 接下来，在DRAM单元的任一侧的沟槽中形成隔离区。 此后，包括含硼沟道区的DRAM单元暴露于由热处理引起的高温以形成支撑装置等。 与基本上不含氮的含氧化物的隔离衬垫相比，含氮化物的隔离衬垫减少了沟道区域中硼的分离。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2002198538A

公开(公告)日：2002-07-12

申请号：JP2001319845

申请日：2001-10-17

Applicant: IBM

Inventor： ADKISSON JAMES W ,  AGNELLO PAUL D ,  ARNE W BALLANTINE ,  DIVAKARUNI RAMA ,  JONES ERIN C ,  NOWAK EDWARD J ,  RANKIN JED H

IPC: H01L29/161 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a dual-gate transistor having a relatively thin epitaxial growth channel. SOLUTION: The epitaxial growth channel is formed, and then a damascene gate is formed, thus forming a silicon-on-insulator(SOI) MOSFET of a dual gate. In the dual-gate MOSFET, a narrow channel should be provided, thus increasing a current drive per layout width, and achieving low out conductance.