公开(公告)号：JPH0817848A

公开(公告)日：1996-01-19

申请号：JP15598295

申请日：1995-06-22

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： FERLA GIUSEPPE ,  FRISINA FERRUCCIO

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/10 ,  H01L29/739

Abstract: PURPOSE: To ignore the base series resistance of a parasitic perpendicular bipolar transistor by adjusting an ion implantation energy so that the peak of the dopant concentration of a heavily doped part of a body region is located on the lower side of a source region than the surface of a semiconductor layer. CONSTITUTION: With an insulation gate layer 10 on the surface of a semiconductor layer 3 as a mask, a first impurity is ion-implanted with an energy in a specific thickness from the surface of the semiconductor layer 3 and is thermally diffused, thus forming a body region 2 consisting of a first greatly doped part 5 that is nearly aligned to both edges of the insulation layer 10 and a horizontal diffusion part 6 at the lower side of the insulation layer 10. The second impurity is ion-implanted selectively into the body region 2 in a pair, thus forming an annular source 7 that is aligned to both edges of the insulation layer 10, thus forming the greatly doped part 5 of the first impurity so that it is located at the lower side of the annular source region 7 and ignoring the base series resistance of a parasitic perpendicular bipolar transistor.

公开(公告)号：JPH07321321A

公开(公告)日：1995-12-08

申请号：JP11716895

申请日：1995-05-16

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAERE ZANBURANO

IPC: H01L27/08 ,  H01L21/336 ,  H01L21/76 ,  H01L27/088 ,  H01L29/78

Abstract: PURPOSE: To prevent the latch-up of the parasitic SCR of a PIC consisting of a vertical-type IGBT and a MOSFET for drive and control. CONSTITUTION: An N -type epitaxial layer 2 is grown on a P -type semiconductor substrate 3 so that an N -type buffer layer 4 is placed between them. A plurality of cells 1 consisting of a deep-P -type layer 40, a shallow N -type layer 6, a poly Si gate 7 being formed on a thin gate oxide film 8 are connected in parallel by a source electrode metal layer 10 according to the amount of power, and an IGBT part where a metal layer 11 is used as a contact electrode is constituted. Also, a MOSFET for drive and control consisting of a source electrode 21, a drain electrode 24, and a gate 20 is formed in a P-type well 15, is surrounded by a deep P -type layer annular region 13 and a P -type-buried region 12, and is completely separated from the IGBT region, thus preventing the latch-up of a parasitic SCR. Also, the same effect can be expected when P-type and the N-type materials are selected inversely.

公开(公告)号：JPH07221346A

公开(公告)日：1995-08-18

申请号：JP27969094

申请日：1994-10-20

Applicant: CONS RIC MICROELETTRONICA

Inventor： SARUBATOORE YUUGO KANPISAANO ,  SARUBATOORE RONBARUDO ,  JIYUSETSUPE FUERURA ,  ARUBERUTO PORUMAN ,  JIERURASU NIKORAASU FUAN DEN H

IPC: H05B33/10 ,  H01L21/265 ,  H01L33/34 ,  H05B33/12 ,  H05B33/18 ,  H01L33/00

Abstract: PURPOSE: To provide silicon using electroluminescent material as a base and a semiconductor device which is clear of conventional technical problems. CONSTITUTION: Electroluminescent material and a semiconductor electroluminescent device include a mixture layer 3 formed by mixing silicon oxides doped with rare earth element ions so as to allow the material and the device to emit light at room temperature. Electroluminescence is caused by the rare earth element ions. An implant having group V or group III element of the periodic table of elements is supplied to a PN junction 3. The requirement for the obtained structure is that it should be heat-treated at a temperature ranging from 400 deg.C to 1100 deg.C.

公开(公告)号：JPH07202606A

公开(公告)日：1995-08-04

申请号：JP19427394

申请日：1994-08-18

Applicant: CONS RIC MICROELETTRONICA

Inventor： NATAARE AIETSURO ,  SERUJIO PARAARA ,  SARUBUATOORE SUKIATSUCHIANOOSE

IPC: H03G11/00 ,  H03K17/0812 ,  H03K17/082 ,  H03K17/16

Abstract: PURPOSE: To stabilize an open ring device by reducing its gain and to smoothly reduce a load current independently of the magnitude of its increase by introducing a feedback circuit block. CONSTITUTION: A limiter circuit for a maximum current to be passed from a power transistor(TR) T'p to a load ZL connected to the TR T'p is provided with a feedback circuit block 2 in addition to a deviation amplifier 1', a driver stage P' and a detecting means Rs for a load current IL. The block 2 is connected between the control terminal of the TR T'p and a current generator in the amplifier 1'.

公开(公告)号：JPH07202202A

公开(公告)日：1995-08-04

申请号：JP32275894

申请日：1994-12-26

Applicant: CONS RIC MICROELETTRONICA

Inventor： SESAARE RONSHISUBUEERU

IPC: H01L21/52 ,  H01L23/051 ,  H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: PURPOSE: To eliminate the risk of damaging the surface of a semiconductor, even when a contact pressure required for superior electrical contact to a power MOS device is applied. CONSTITUTION: A semiconductor device chip 22 is provided with a dummy cell 11, and the thickness of an oxide layer 7 in dummy cell 11 is made thicker than that of the oxide layer 7 in the residual part of the semiconductor device chip 22, and a polysilicon layer 8 and a metal layer 10 are protruded higher than the residual part of the semiconductor device chip 2, and the pressure applied with a washer 16 is made to be applied to the entire surface of the dummy cell 11.

公开(公告)号：JPH07202199A

公开(公告)日：1995-08-04

申请号：JP30758194

申请日：1994-12-12

Applicant: CONS RIC MICROELETTRONICA

Inventor： PIEERO JIORUJIO FUARITSUKA

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/06 ,  H01L29/78

Abstract: PURPOSE: To prevent a value of clamp voltage from changing, even when a wafer is different by forming a second electrode of a second diode with a second conductivity type first buried region, and forming a first electrode of a second diode with a first conductivity type first doped region. CONSTITUTION: A first diode D1 and a second diode D2, formed in a first conductivity type low doped layer, are provided. The first diode D1 has a first electrode connected to a control electrode of a power semiconductor device and a second electrode connected to a second electrode of the second diode D2, and a first electrode of the second diode D2 is connected to a load drive electrode of the power semiconductor device. Than the second electrode of the second diode D2 is formed with a second conductivity type first buried region 11 buried in the lightly doped layer, and the first electrode of the second diode D2 is formed so as to partially overlap the first buried region 11, with a first conductivity type first doped region 12, extending from the top surface of the semiconductor in the lightly doped layer.

公开(公告)号：JPH07142525A

公开(公告)日：1995-06-02

申请号：JP14487194

申请日：1994-06-27

Applicant: SGS THOMSON MICROELECTRONICS ,  CONS RIC MICROELETTRONICA

Inventor： ANTONIO GURATSUSO ,  ANNTONIO PINTO

IPC: H01L21/60 ,  H01L21/48 ,  H01L21/607 ,  H01L23/495

Abstract: PURPOSE: To attain improvement in quality and reliability by improving a connecting part between a semiconductor chip and the pin of supporting frame by making a wire lead into continuous wire having 1st and 2nd contact bonds arranged on a connecting pin. CONSTITUTION: A semiconductor chip 1 is tied in the central zone of sheet metal 4 while using a solder 3, and the sheet metal 4 is coupled to a connecting pin 7 on the metallic supporting frame by a metal link 5. Besides, a wire lead 8 is connected by bonding the respective connecting pins 7 with correspondent pads 2 on the semiconductor chip 1. Especially, the wire lead 8 is twice bonded 10 and 11 to post leads 6 of respective connecting pins 7 by cascade connection. Such double bonding is extremely effective for reinforcing the quality and reliability of semiconductor device by canceling various limits or defects in conventional techniques.

公开(公告)号：JPH0729914A

公开(公告)日：1995-01-31

申请号：JP14012694

申请日：1994-06-22

Applicant: CONS RIC MICROELETTRONICA

Inventor： FUERUTSUCHIO FURISHINA ,  SARUBUATOORE KOTSUFUA

IPC: H01L21/331 ,  H01L29/06 ,  H01L29/167 ,  H01L29/73 ,  H01L29/732

Abstract: PURPOSE: To increase a base-collector breakdown voltage by a method, wherein a heavily doped P-type layer is formed in a deep lightly doped P-type diffused region which extends into a lightly doped N-type layer from a top surface made of acceptor dopant. CONSTITUTION: An aluminum-doped deep P-type region 3 is extended into an epitaxial layer 2 to a depth of about 30-40 μm from a top surface, and a heavily doped P -type region 4 is extended into the deep P-type region 3 to a depth of about 10 μm from the top surface. A base region is composed of the P -type region 4 and the P-type region 3. Three concentric rings 5, 6 and 7, which are composed of aluminum heavily doped P-type regions, are extended into the epitaxial layer 2 from the top surface. The dopant concentration of the ring 5 is higher than the dopant concentration of the ring 6, and the dopant concentration of the ring 6 is higher than the dopant concentration of the ring 7. With this constitution, a base-collector breakdown voltage is increased.

公开(公告)号：JPH0722851A

公开(公告)日：1995-01-24

申请号：JP9588194

申请日：1994-04-09

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： MILAZZO PATRIZIA ,  BONTEMPO GREGORIO ,  ALZATI ANGELO

IPC: H03F1/02 ,  H02M1/08 ,  H03F3/21 ,  H03K17/00 ,  H03K17/0412 ,  H03K17/687

Abstract: PURPOSE: To turn steady current consumption to zero without losing characteristics by providing a control circuit with a switch for blocking a current from a discharge current oscillator having control node capacitance when a power transistor(TR) is in an OFF state. CONSTITUTION: When a power TR PW is in an OFF state, the gate voltage of a TR M5 is also reduced. In the case of a switch OFF phase, the resistance of the TR M5 is increased and mismatch between currents I1, I2 is generated. The generation of a mis-matching trouble can be removed by determining the dimensions of the TR M5 so that large mismatch is generated when the power TR PW is slipped out of the saturation. Thereby the TR M5 operates as a switch to be opened when the gate voltage of the power TR PW is dropped less than the threshold voltage of the TR M5 and turns off a branch I2. Consequently the speed characteristics of the current oscillator I2 and the switch M5 can be held.

公开(公告)号：JPH0715006A

公开(公告)日：1995-01-17

申请号：JP8050794

申请日：1994-04-19

Applicant: CONS RIC MICROELETTRONICA

Inventor： RAFUAERU ZANBURANO

IPC: H01L29/78 ,  H01L27/02 ,  H01L27/04

Abstract: PURPOSE: To provide an integrated structure protective device suitable for protecting a logic level power MOS device during a static discharge. CONSTITUTION: An integrated structure protective device suitable for protecting a power MOS device from a static discharge is provided with a junction diode 9. The junction diode 9 is surrounded by a second-conductivity-type intrinsic region 11 and is provided with a first electrode comprising a first-conductivity- type heavily doped region 12 constituting the junction diode 9. The first electrode is surrounded by a second-conductivity-type heavily doped deep intrinsic region 10. The heavily doped region 12 is connected to a polycrystalline silicon gate layer 7 constituting the gate of the power MOS device and connects the heavily doped deep intrinsic region 10 to the source region 6 of the power MOS device.