公开(公告)号：KR1020150086751A

公开(公告)日：2015-07-29

申请号：KR1020140006792

申请日：2014-01-20

Applicant: 한국전자통신연구원 ,  단국대학교 산학협력단

Inventor： 양일석 ,  남은수 ,  이명래 ,  구용서

IPC: H01L27/04

Abstract: 본발명은정전기방전보호회로에관한것이다. 본발명의정전기방전보호회로는기판상에형성된딥 N웰, 딥 N웰상의우측에형성되고, 제 1 P+확산영역, 제 1 N+확산영역, 제 2 P+확산영역, 및플로팅 P+확산영역을포함하는제 1 P웰, 딥 N웰상에형성되고, 제 1 P웰의좌측에위치하고, 플로팅 N+확산영역, 제 3 P+확산영역, 제 2 N+확산영역을포함하는 N웰, 및딥 N웰상에형성되고, 제 N웰의좌측에위치하고, 제 4 P+확산영역과제 3 N+ 확산영역중 하나를포함하는제 2 P웰을포함하고, N웰은제 1 P웰과제 2 P웰사이에위치하고, N웰과제 2 P웰사이의간격은 N웰과제 1 P웰사이의간격보다좁고, 제 1 P+확산영역과제 1 N+확산영역은캐소드에연결되고, 제 3 P+확산영역과제 2 N+확산영역은애노드에연결되고, 제 2 P+확산영역과제 4 P+확산영역은상호간에연결되는것을특징으로한다.

Abstract translation: 静电放电保护电路技术领域本发明涉及静电放电保护电路。 本发明的静电放电保护电路包括：在衬底上形成的深N阱; 第一P阱形成在深N阱的右侧，并且包括第一P +扩散区域，第一N +扩散区域，第二P +扩散区域和浮置P +扩散区域; N阱形成在深N阱上，位于第一P阱的左侧，并且包括浮置N +扩散区域，第三P +扩散区域和第二N +扩散区域; 以及形成在深N阱上的第二P阱，位于N阱的左侧，并且包括第四P +扩散区域和第三N +扩散区域中的一个。 N井位于第一个P井和第二个P井之间。 N阱和第二P阱之间的间隔比N阱和第一P阱之间的间隔窄。 第一P +扩散区域和第一N +扩散区域连接到阴极。 第三P +扩散区域和第二N +扩散区域连接到阳极。 第二P +扩散区域和第四P +扩散区域相互连接。

公开(公告)号：KR1020140075946A

公开(公告)日：2014-06-20

申请号：KR1020120143702

申请日：2012-12-11

Applicant: 한국전자통신연구원

Inventor： 임종원 ,  안호균 ,  장우진 ,  강동민 ,  김성일 ,  이상흥 ,  윤형섭 ,  주철원 ,  김해천 ,  문재경 ,  남은수

IPC: H01L29/778 ,  H01L21/335

CPC classification number: H01L29/778 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66431

Abstract: A high electron mobility transistor is provided. The transistor includes a source electrode and a drain electrode disposed on a substrate to be spaced apart; a T-shaped gate electrode disposed between the source electrode and the drain electrode on the substrate; and a plurality of insulating films interposed between the substrate and the T-shaped gate electrode. The plurality of insulating films is composed of a first insulating film, a second insulating film, and a third insulating film. The third insulating film is interposed between the substrate and the head part of the T-shaped gate electrode to be in contact with the leg part of the T-shaped gate electrode. The second insulating film is interposed between the substrate and the head part of the T-shaped gate electrode to be in contact with the third insulating film. The first insulating film and the third insulating film stacked in order are interposed between the substrate and the head part of the T-shaped gate electrode to be in contact with the second insulating film.

Abstract translation: 提供高电子迁移率晶体管。 晶体管包括设置在基板上的源电极和漏电极以被间隔开; 设置在基板上的源电极和漏电极之间的T字栅电极; 以及插入在所述基板和所述T形栅电极之间的多个绝缘膜。 多个绝缘膜由第一绝缘膜，第二绝缘膜和第三绝缘膜构成。 第三绝缘膜插入到基板和T形栅电极的头部之间，以与T形栅电极的腿部接触。 第二绝缘膜插入到基板和T形栅电极的头部之间以与第三绝缘膜接触。 按顺序堆叠的第一绝缘膜和第三绝缘膜介于基板和T形栅电极的头部之间以与第二绝缘膜接触。

公开(公告)号：KR1020140048026A

公开(公告)日：2014-04-23

申请号：KR1020130029769

申请日：2013-03-20

Applicant: 한국전자통신연구원

Inventor： 민병규 ,  고상춘 ,  임종원 ,  안호균 ,  윤형섭 ,  문재경 ,  남은수

IPC: H01L21/3205 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/535

Abstract: A semiconductor device according to the concept of the present invention may include a substrate having a lower via hole; an epi layer which has an opening part for exposing the upper surface of the substrate; a semiconductor chip which is provided on the upper surface of the substrate and includes a first electrode, a second electrode, and a third electrode; an upper metal layer connected to the first electrode; a support plate which is arranged on the upper metal layer and has an upper via hole; an upper pad which is arranged on the support substrate and is extended to the inner part of the upper via hole; a lower pad which is arranged in the opening pad and is connected to the second electrode; and a lower metal layer which covers the lower surface of the substrate and is connected to the lower pad through the lower via hole.

Abstract translation: 根据本发明的概念的半导体器件可以包括具有下通孔的衬底; 外延层，其具有用于使基板的上表面露出的开口部; 半导体芯片，其设置在所述基板的上表面，并且包括第一电极，第二电极和第三电极; 连接到第一电极的上金属层; 支撑板，其设置在上金属层上并具有上通孔; 上垫，其布置在所述支撑基板上并延伸到所述上通孔的内部; 下垫，其布置在所述开口垫中并连接到所述第二电极; 以及覆盖基板的下表面并通过下通孔连接到下焊盘的下金属层。

公开(公告)号：KR1020140001299A

公开(公告)日：2014-01-07

申请号：KR1020120067891

申请日：2012-06-25

Applicant: 한국전자통신연구원

Inventor： 오명숙 ,  민봉기 ,  심재식 ,  김기수 ,  이윤정 ,  권용환 ,  남은수

IPC: G01S17/89 ,  G01S17/02

CPC classification number: G01J1/42 ,  G01S7/481 ,  G01S7/4863 ,  G01S7/4914 ,  G01S17/42 ,  G01S17/89

Abstract: The present invention relates to an apparatus for acquiring three dimensional information for detecting information of wide area by making an array of photo detectors, in measuring a three dimensional image by that a light of a laser radar for three dimensional image measurement is reflected from a target object and then is incident on the photo detector through a light receiving lens. The apparatus for acquiring three dimensional information includes: a light source part for generating a light signal of fixed wavelength band; a light transmission optical lens part which is prepared on the path of the light signal and irradiates the light signal outputted from the light source in a parallel or constant angle; a light scanning part for scanning the light outputted from the light transmission optical lens to the surface of an object to measure; a light receiving optical lens part for collecting the light reflected from the surface of the object; and a light detection part for converting the light signal collected by making an array of more than one photo detector for a light receiving part to be gathered at the center, into a current signal respectively.

Abstract translation: 本发明涉及一种用于通过制作光电检测器的阵列来获取用于检测广域的信息的三维信息的装置，用于通过用于三维图像测量的激光雷达的光从目标反射来测量三维图像 然后通过光接收透镜入射到光电检测器上。 用于获取三维信息的装置包括：用于产生固定波长带的光信号的光源部分; 光传输光学透镜部件，其在光信号的路径上准备并以平行或恒定的角度照射从光源输出的光信号; 光扫描部，用于将从光透射光学透镜输出的光扫描到待测物体的表面; 光接收光学透镜部分，用于收集从物体表面反射的光; 以及光检测部分，用于通过将用于待聚集在中心的光接收部分的多于一个光检测器的阵列分别收集的光信号转换成电流信号。

公开(公告)号：KR1020130093996A

公开(公告)日：2013-08-23

申请号：KR1020120015292

申请日：2012-02-15

Applicant: 한국전자통신연구원

Inventor： 이종민 ,  민병규 ,  김성일 ,  윤형섭 ,  문재경 ,  남은수

IPC: H03H7/38 ,  H03F3/20 ,  H01G5/019

CPC classification number: H01L21/8222 ,  H01G7/00 ,  H01L27/0647 ,  H01L27/0658 ,  H01L29/93 ,  H03F1/565 ,  H03F3/21 ,  H03F2200/36 ,  H03F2200/378 ,  H03F2200/387 ,  H03F2200/391 ,  H03H7/38 ,  Y10T29/43

Abstract: PURPOSE: An impedance matching circuit including passive elements for controlling the matching property, an amplification circuit and a manufacturing method of a variable capacitor are provided to modify the characteristic value of passive elements included in the multi-staged impedance matching circuit, so that a broadband matching realizes. CONSTITUTION: A first variable inductor part (L1) is connected between the output terminal of a first node (N1) and an amplifying unit (AMP). A second variable inductor part (L2) is connected between the first node and a second Node (N2). The inductance value of the first variable inductor part and the second variable inductor part is determined according to the number and the length of wires. A first variable capacitor portion (C1) is connected between the first node and a ground voltage platform. A second variable capacitor portion (C2) is connected between the second node and the ground voltage platform. [Reference numerals] (AMP) Power amplifying unit

Abstract translation: 目的：提供一种阻抗匹配电路，其包括用于控制匹配特性的无源元件，放大电路和可变电容器的制造方法，以修改包括在多级阻抗匹配电路中的无源元件的特性值，使得宽带 匹配实现。 构成：第一可变电感器部分（L1）连接在第一节点（N1）的输出端和放大单元（AMP）之间。 第二可变电感器部分（L2）连接在第一节点和第二节点（N2）之间。 根据导线的数量和长度确定第一可变电感器部分和第二可变电感器部分的电感值。 第一可变电容器部分（C1）连接在第一节点和地电压平台之间。 第二可变电容器部分（C2）连接在第二节点和地电压平台之间。 （附图标记）（AMP）功率放大单元

公开(公告)号：KR1020130067613A

公开(公告)日：2013-06-25

申请号：KR1020110134353

申请日：2011-12-14

Applicant: 한국전자통신연구원

Inventor： 김덕준 ,  김종회 ,  최중선 ,  윤천주 ,  최광성 ,  권용환 ,  남은수

IPC: G02B6/122

CPC classification number: G02B6/1228 ,  G02B6/126

Abstract: PURPOSE: A core and an optical wave guide are provided to reduce the light connection loss between discontinuous optical wave guides which exist on a same substrate. CONSTITUTION: A core(100) is comprised of the followings: a first optical wave progressing unit(109) which has a first light receiving width; a first optical wave discontinuous unit(106) which has a second light receiving width which is smaller than the first light receiving width; a first taper configuration unit(105) which connects with the first optical wave progressing unit and the first optical wave discontinuous unit, and in which the light receiving width becomes narrower from the first optical wave progressing unit to the first optical wave discontinuous unit; a second light progressing unit(110) which has a third light receiving width; a second optical wave discontinuous unit(107) which has a fourth light receiving width which is smaller than the third light receiving width and the first light receiving width; and a second taper configuration unit(108) which connects with the second light progressing unit and the second optical wave discontinuous unit, and in which the light receiving width becomes narrower from the second optical wave progressing unit to the second optical wave discontinuous unit.

Abstract translation: 目的：提供芯和光波导，以减少存在于同一基板上的不连续光波导之间的光连接损耗。 构成：芯（100）包括：第一光波进行单元（109），其具有第一光接收宽度; 第一光波不连续单元（106），其具有小于第一光接收宽度的第二光接收宽度; 第一锥形配置单元，其与第一光波进行单元和第一光波不连续单元连接，并且其中光接收宽度从第一光波进行单元变窄到第一光波不连续单元; 具有第三光接收宽度的第二光进行单元（110） 第二光波不连续单元（107），其具有小于所述第三光接收宽度和所述第一光接收宽度的第四光接收宽度; 以及第二锥形配置单元，其与第二光进行单元和第二光波不连续单元连接，并且其中光接收宽度从第二光波进行单元变窄到第二光波不连续单元。

公开(公告)号：KR1020130066934A

公开(公告)日：2013-06-21

申请号：KR1020110133715

申请日：2011-12-13

Applicant: 한국전자통신연구원

Inventor： 윤형섭 ,  민병규 ,  이종민 ,  김성일 ,  강동민 ,  안호균 ,  임종원 ,  문재경 ,  남은수

IPC: H01L21/338 ,  H01L29/812

CPC classification number: H01L29/0649 ,  H01L21/28593 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7786

Abstract: PURPOSE: A semiconductor device including a step gate electrode and a manufacturing method thereof are provided to increase a breakdown voltage by using optical photoresist and two nitride layers. CONSTITUTION: A cap layer(211) is formed on a semiconductor substrate. An active area is formed by etching a part of the cap layer. A resist pattern is formed on the active area and the cap layer. A step gate electrode(225) is formed by depositing heat-resistant metal. An insulation layer(227) is deposited by removing a gate head pattern.

Abstract translation: 目的：提供包括步进栅电极及其制造方法的半导体器件，以通过使用光致抗蚀剂和两个氮化物层来增加击穿电压。 构成：在半导体衬底上形成覆盖层（211）。 通过蚀刻盖层的一部分形成有源区。 在有源区域和盖层上形成抗蚀剂图案。 通过沉积耐热金属形成步进栅电极（225）。 通过去除栅极头图案来沉积绝缘层（227）。

公开(公告)号：KR101268547B1

公开(公告)日：2013-05-28

申请号：KR1020090124872

申请日：2009-12-15

Applicant: 한국전자통신연구원

Inventor： 최중선 ,  권용환 ,  윤천주 ,  김종회 ,  최광성 ,  남은수

IPC: G02B6/38

CPC classification number: G02B6/3825 ,  G02B6/3894

Abstract: 본발명은어뎁터어셈블리및 이를이용한광섬유길이차이를보상하는방법에관한것이다. 본발명의어뎁터어셈블리는적어도하나의광통신수단이연결될수 있는제1 어뎁터와, 적어도하나의다른광통신수단이연결될수 있으며상기제1 어뎁터와결합되는제2 어뎁터와, 그리고상기제1 및제2 어뎁터사이에샌드위치되어상기광통신수단들사이에서광신호의전송경로를제공하는부재를포함할수 있다. 본발명에의하면, 상기부재에의해광섬유의길이장단에따른광신호전송경로차이가보상된다.

公开(公告)号：KR1020120068599A

公开(公告)日：2012-06-27

申请号：KR1020100130291

申请日：2010-12-17

Applicant: 한국전자통신연구원

Inventor： 안호균 ,  임종원 ,  윤형섭 ,  민병규 ,  이상흥 ,  김해천 ,  남은수

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/7783

Abstract: PURPOSE: A field effect transistor and a manufacturing method thereof are provided to control an insulation film property of the lower side of an electric field electrode by controlling the thickness of an insulation film on the lower side of each electric field electrode in a field effect transistor. CONSTITUTION: A source electrode, a drain electrode, and a gate electrode are formed on the upper side of a semiconductor substrate(20). A multilayer electric field electrode pattern with a different exposure layer with an opening unit is formed by depositing and patterning a multilayer photosensitive film on the upper side of an insulation film(27). An insulation film with a different step is formed by an insulation film etching process using an electric field electrode pattern as an etch mask. An electric field electrode(30a,30b,30c) is formed on the upper side of the insulation film by lifting off a metal layer after the metal layer is deposited by using the electric field pattern.

Abstract translation: 目的：提供场效应晶体管及其制造方法，以通过控制场效应晶体管中每个电场电极下侧的绝缘膜的厚度来控制电场电极的下侧的绝缘膜性质 。 构成：在半导体衬底（20）的上侧形成源电极，漏电极和栅电极。 通过在绝缘膜（27）的上侧上沉积和图案化多层感光膜，形成具有开口单元的不同曝光层的多层电场电极图案。 通过使用电场电极图案作为蚀刻掩模的绝缘膜蚀刻工艺形成具有不同台阶的绝缘膜。 通过使用电场图案沉积金属层之后，通过剥离金属层，在绝缘膜的上侧形成电场电极（30a，30b，30c）。

公开(公告)号：KR1020120068337A

公开(公告)日：2012-06-27

申请号：KR1020100129923

申请日：2010-12-17

Applicant: 한국전자통신연구원

Inventor： 윤천주 ,  권용환 ,  김덕준 ,  김종회 ,  최중선 ,  최광성 ,  남은수

IPC: H04B10/145 ,  H04B10/148

CPC classification number: H04B10/548 ,  H04B10/0775 ,  H04B10/588 ,  H04B10/613 ,  H04B10/6165 ,  H04L27/2096 ,  H04L27/2613 ,  H04L27/2657 ,  H04L27/2675 ,  H04L27/2692 ,  H04L27/2697

Abstract: PURPOSE: A method and a device for transmitting and receiving coherent optical orthogonal frequency division multiplexing(OFDM) are provided to efficiently compensate phase noises although a system uses a light source with a wide line width for OFDM signals with long symbol lengths. CONSTITUTION: A transmission OFDM digital signal processing part(210) outputs in-phase digital signals and quadrature digital signals. A digital to analog converter(220) converts the in-phase digital signals and the quadrature digital signals into analog signals. An adder(230) adds additional pilot tone signals to each analog signal. An optical in-phase/quadrature modulator(240) outputs coherent optical OFDM signals containing the additional pilot tone signals by upwardly converting the analog signals based on additional pilot tone signal added in-phase components and quadrature components.

Abstract translation: 目的：提供一种用于发送和接收相干光正交频分复用（OFDM）的方法和设备，以便有效地补偿相位噪声，尽管系统对具有长符号长度的OFDM信号使用具有宽线宽的光源。 构成：发送OFDM数字信号处理部（210）输出同相数字信号和正交数字信号。 数模转换器（220）将同相数字信号和正交数字信号转换为模拟信号。 加法器（230）向每个模拟信号添加附加的导频音信号。 光同相/正交调制器（240）通过基于添加的同相分量和正交分量的附加导频音信号向上转换模拟信号来输出包含附加导频音信号的相干光OFDM信号。