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    91.
    发明专利
    未知

    公开(公告)号：DE50312210D1

    公开(公告)日：2010-01-21

    申请号：DE50312210

    申请日：2003-10-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

    IPC: H01L27/12 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108

    Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.

    92.
    发明专利
    未知

    公开(公告)号：DE59813900D1

    公开(公告)日：2007-03-22

    申请号：DE59813900

    申请日：1998-08-26

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  RAMCKE TIES ,  RISCH LOTHAR

    IPC: G06F7/501 ,  H01L29/76 ,  G06F7/50 ,  G06F7/505 ,  H01L29/66 ,  H03K17/00 ,  H03K19/02

    Abstract: At least one single-electron transistor is provided in a circuit configuration having single-electron components, and is connected between a first main node and a second main node. The first main node is capacitively connected between a first operating voltage connection and a second operating voltage connection. The gate electrode of the single-electron transistor is connected to a control voltage connection. The circuit configuration is suitable for logic operations on binary numbers, whose digits are stored at the first and second main nodes.

    93.
    发明专利
    未知

    公开(公告)号：DE50013984D1

    公开(公告)日：2007-03-08

    申请号：DE50013984

    申请日：2000-11-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SCHLOESSER TILL

    IPC: H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

    Abstract: The invention relates to a transistor that is provided with a first source/drain area (S/D 1 ), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2 ) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D 1 ). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D 1 ) are arranged in the insulating area. The second source/drain area (S/D 2 ) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.

    96.
    发明专利
    未知

    公开(公告)号：DE102005024951A1

    公开(公告)日：2006-12-14

    申请号：DE102005024951

    申请日：2005-05-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  SPECHT MICHAEL ,  STAEDELE MARTIN ,  LUYKEN JOHANNES

    IPC: H01L27/108 ,  G11C11/40

    Abstract: A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.

    98.
    发明专利
    未知

    公开(公告)号：DE102004060171A1

    公开(公告)日：2006-06-14

    申请号：DE102004060171

    申请日：2004-12-14

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  SPECHT MICHAEL

    IPC: H01L27/115 ,  H01L21/8247

    Abstract: The memory cell array comprises a plurality of parallel fins provided as bitlines arranged at a distance of down to about 40 nm from one another and having a lateral dimension of less than about 30 nm, subdivided into pairs of adjacent first and second fins. A charge-trapping memory layer sequence is arranged on the fins. Wordlines are arranged across the fins, and source/drain regions are located in the fins between the wordlines and at the ends of the fins. There are preferably self-aligned contact areas of the source/drain regions at the ends of the fins, each contact area being common to the fins of one of said pairs. Select transistors and select lines are provided for the first and second fins individually to enable a separate addressing of the memory cells.

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