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    91.
    发明专利
    未知

    公开(公告)号：DE69930238D1

    公开(公告)日：2006-05-04

    申请号：DE69930238

    申请日：1999-06-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  OHBA ,  CARRERA MARCELLO

    IPC: G11C16/06 ,  G11C16/12 ,  G11C8/00 ,  G11C8/08 ,  G11C11/56 ,  H03K19/173

    Abstract: The row decoder includes, for each word line (WL) of the memory (2), a respective biasing circuit (54) receiving at the input a row selection signal (SR ) switching, in preset operating conditions, between a supply voltage (VCC) and a ground voltage (VGND) and supplying at the output a biasing signal (R ) for the respective word line (WL) switching between a first operating voltage (VPC), in turn switching at least between the supply voltage (VCC) and a programming voltage (VPP) higher than the supply voltage (VCC), and a second operating voltage (VNEG), in turn switching at least between the ground voltage (VGND) and an erase voltage (VERN) lower than the ground voltage (VGND). Each biasing circuit (54) includes a level translator circuit (58) receiving at the input the row selection signal (SR ) and supplying as output a control signal (CM ) switching between the first and the second operating voltages (VPC, VNEG) and an output driver circuit (60) receiving as input the control signal (CM ) and supplying at the output the biasing signal (R ).

    94.
    发明专利
    未知

    公开(公告)号：ITMI20021486A1

    公开(公告)日：2004-01-05

    申请号：ITMI20021486

    申请日：2002-07-05

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  MOTTA ILARIA ,  CAPOVILLA MARCO

    IPC: G11C5/14 ,  G11C8/08 ,  G11C16/12

    Abstract: Voltage booster device (3) such as to selectively assume an active status and a stand-by status, said device comprising: a first terminal (15) such as to assume a respective electric potential and associated to a first capacitor (16), a second terminal (10) associated to a second capacitor (11) and selectively connectable to the first terminal (15), characterised in that it also comprises circuital means (100) for discharging the first capacitor thus reducing in module the electrical potential of the first terminal (15), the circuital means being activated to functioning when said device in the stand-by status and the second terminal (10) is disconnected from said first terminal (15).

    95.
    发明专利
    未知

    公开(公告)号：IT1320666B1

    公开(公告)日：2003-12-10

    申请号：ITTO20000892

    申请日：2000-09-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SACCO ANDREA ,  KHOURI OSAMA ,  MICHELONI RINO ,  TORELLI GUIDO

    IPC: G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C8/14 ,  G11C16/08

    Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

    96.
    发明专利
    未知

    公开(公告)号：IT1319037B1

    公开(公告)日：2003-09-23

    申请号：ITMI20002337

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  GREGORI STEFANO ,  PIERIN ANDREA ,  MICHELONI RINO ,  CORONINI SERGIO ,  TORELLI GUIDO

    IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C27/00

    Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

    97.
    发明专利
    未知

    公开(公告)号：IT1318158B1

    公开(公告)日：2003-07-23

    申请号：ITMI20001585

    申请日：2000-07-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  PIERIN ANDREA ,  MICHELONI RINO ,  GREGORI STEFANO ,  TORELLI GUIDONO ,  SANGALLI MIRIAM

    IPC: G11C16/08

    Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.

    98.
    发明专利
    未知

    公开(公告)号：ITMI20002337A1

    公开(公告)日：2002-04-29

    申请号：ITMI20002337

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TORELLI GUIDO ,  MICHELONI RINO ,  KHOURI OSAMA ,  PIERIN ANDREA ,  GREGORI STEFANO ,  CORONINI SERGIO

    IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C27/00

    Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

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