公开(公告)号：WO2008014157A3

公开(公告)日：2008-03-20

申请号：PCT/US2007073746

申请日：2007-07-18

Applicant: HONEYWELL INT INC ,  JACKSON MERRILL M ,  HUMPHREY DAVID

Inventor： JACKSON MERRILL M ,  HUMPHREY DAVID

IPC: C22C13/00 ,  B23K35/26 ,  C09D5/18 ,  H01L23/495 ,  H05K3/34

CPC classification number: C22C13/00 ,  C09D5/185 ,  H01L23/49582 ,  H01L23/49586 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/181 ,  H05K3/244 ,  H05K3/3436 ,  H05K2201/10689 ,  H05K2201/10909 ,  Y02P70/613 ,  Y10T428/12556 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electrical component includes a conductive substrate (18), a tin layer (19) formed on the substrate, and a coating (22) of a foam formed on the tin layer to impede tin whisker growth, the coating comprising a foam (28) having voids (30) dispersed therethrough. A method for impeding tin whisker growth from a tin plating or finish formed over an electrical component includes covering the tin plating or finish with a coating of intumescent paint, and thereafter expanding the intumescent paint into a foam having voids dispersed therethrough.

Abstract translation: 一种电子元件包括导电基底（18），在基底上形成的锡层（19）以及在锡层上形成的用于阻止锡晶须生长的泡沫涂层（22），该涂层包括泡沫（28） 具有分散在其中的空隙（30）。 一种用于阻止锡电镀层或在电子部件上形成的饰面的锡晶须生长的方法包括用膨胀型涂料涂覆锡镀层或涂饰层，然后将膨胀型涂料扩展成具有分散在其中的空隙的泡沫。

公开(公告)号：WO2006111421A1

公开(公告)日：2006-10-26

申请号：PCT/EP2006/003755

申请日：2006-04-24

Applicant: DBK DAVID + BAADER GMBH ,  GSCHWIND, Thomas ,  BAUER, Hans-Peter

Inventor： GSCHWIND, Thomas ,  BAUER, Hans-Peter

IPC: H01H85/10

CPC classification number: H05K1/0201 ,  H01H37/761 ,  H01H85/10 ,  H01H2085/0275 ,  H01H2085/0555 ,  H05K3/308 ,  H05K2201/10181 ,  H05K2201/10878 ,  H05K2201/10909

Abstract: Eine Schmelzsicherung für Leiterplattenmontage besitzt Anschlüsse, die mit Leiterbahnen auf der Leiterplatte elektrisch verbindbar sind, sowie mindestens eine leitfähige und schmelzbare Verbindung zwischen den Anschlüssen. Sie ist so gestaltet, dass sie kostengünstig einstückig aus Blech oder leitfähigem Kunststoff gefertigt werden kann. Die Schmelzsicherung kann eine Überhitzung einer Heizvorrichtung, in der sie eingesetzt wird, verhindern, indem sie angepasst ist, die mindestens eine leitfähige und schmelzbare Verbindung bei thermischer Überlast zu trennen.

Abstract translation: 一种用于电路板组件保险丝具有电连接到电路迹线在印刷电路板上的端子，和至少一个导电可熔链路和端子之间。 它被设计成使得它可以在由金属板或导电塑料单件被廉价地制造。 熔丝可以防止在其被使用由适于以分离至少一个导电可熔链路和下热过载的加热器的过热。

公开(公告)号：WO2005074026A3

公开(公告)日：2005-10-06

申请号：PCT/US2005001999

申请日：2005-01-21

Applicant: ENTHONE ,  XU CHEN ,  ZHANG YUN ,  FAN CHONGLUN ,  KHASELEV OSCAR ,  ABYS JOSEPH A ,  WALCH ERIC ,  KLEINFELD MARLIES ,  ECKERT HANS ULLRICH

Inventor： XU CHEN ,  ZHANG YUN ,  FAN CHONGLUN ,  KHASELEV OSCAR ,  ABYS JOSEPH A ,  WALCH ERIC ,  KLEINFELD MARLIES ,  ECKERT HANS ULLRICH

IPC: C25D5/12 ,  H01L23/495 ,  H01R4/02 ,  H01R13/03 ,  H05K3/34

CPC classification number: H01L23/49582 ,  C25D5/12 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01327 ,  H01L2924/15747 ,  H01L2924/19041 ,  H01R4/02 ,  H01R13/03 ,  H05K3/3426 ,  H05K2201/10909 ,  Y02P70/613 ,  Y10T428/12722 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A method for reducing whisker formation and preserving solderability in tin coatings over metal features of electronic components. The tin coating has internal tensile stress and is between about 0.5 m and about 4.0 m in thickness. There is a nickel-based layer under the tin coating.

Abstract translation: 一种减少电子部件的金属特征的方法，用于减少锡涂层中的晶须形成和保持锡涂层的可焊性。 锡涂层具有内部拉伸应力，厚度在约0.5μm至约4.0μm之间。 在锡涂层下面有一个镍基层。

公开(公告)号：WO98050954A1

公开(公告)日：1998-11-12

申请号：PCT/US1998/009442

申请日：1998-05-08

IPC: B23K20/00 ,  C25D7/12 ,  G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  H01L21/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L21/603 ,  H01L21/66 ,  H01L23/48 ,  H01L23/485 ,  H01L23/49 ,  H01L23/498 ,  H01L25/065 ,  H01L25/16 ,  H05K1/14 ,  H05K3/20 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40

CPC classification number: B23K20/004 ,  B23K2101/40 ,  C25D7/12 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/48 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13169 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K1/141 ,  H05K3/20 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/368 ,  H05K3/4015 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  H01L2924/00014

Abstract: High density packaging of semiconductor devices on an interconnection substrate is achieved by stacking bare semiconductor devices (402, 404, 406, 408) atop one another so that an edge portion of a semiconductor device extends beyond the semiconductor device that it is stacked atop. Elongate interconnection elements (422, 424, 426, 428) extend from the bottommost one of the semiconductor devices, and from the exposed edge portions of the semiconductor devices stacked atop the bottommost semiconductor device. Free-ends of the elongate interconnection elements make electrical contact with terminals of an interconnection substrate (430), such as a PCB. The elongate interconnection elements extending from each of the semiconductor devices are sized so as to reach the terminals of the PCB, which may be plated through holes (432, 434, 436, 438). The elongate interconnection elements are suitably resilient contact structures, and may be composite interconnection elements comprising a relatively soft core (e.g., a gold wire) and a relatively hard overcoat (e.g., a nickel plating).

Abstract translation: 通过将半导体器件（402,404,406,408）彼此顶起堆叠来实现半导体器件在互连衬底上的高密度封装，使得半导体器件的边缘部分延伸超过其顶部堆叠的半导体器件。 细长的互连元件（422,424,426,428）从半导体器件的最底端延伸，并且从半导体器件的暴露的边缘部分堆叠在最底层的半导体器件的顶部。 细长互连元件的自由端与诸如PCB的互连衬底（430）的端子电接触。 从每个半导体器件延伸的细长互连元件的尺寸被设计成到达可以通过孔（432,434,436,438）电镀的PCB的端子。 细长互连元件是合适的弹性接触结构，并且可以是包括相对软的芯（例如，金线）和相对硬的外涂层（例如镀镍）的复合互连元件。

公开(公告)号：WO1996015459A1

公开(公告)日：1996-05-23

申请号：PCT/US1995014885

申请日：1995-11-15

Applicant: FORMFACTOR, INC.

Inventor： FORMFACTOR, INC. ,  KHANDROS, Igor, Y. ,  MATHIEU, Gaetan, L. ,  ELDRIDGE, Benjamin, N. ,  GRUBE, Gary, W.

IPC: G01R01/073

CPC classification number: H05K7/1069 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D7/12 ,  C25D21/02 ,  G01R1/0483 ,  G01R31/2863 ,  H01L21/288 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/67138 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/13657 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45644 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48644 ,  H01L2224/48699 ,  H01L2224/48844 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4015 ,  H05K3/4092 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2224/48744 ,  H01L2924/20751 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/00015 ,  H01L2924/2075 ,  H01L2924/20754

Abstract: Resilient contact structures (430) are mounted directly to bond pads (410) on semiconductor dies (402a, 402b), prior to the dies (402a, 402b) being singulated (separated) from a semiconductor wafer. This enables the semiconductor dies (402a, 402b) to be exercised (e.g., tested and/or burned-in) by connecting to the semiconductor dies (702, 704) with a circuit board (710) or the like having a plurality of terminals (712) disposed on a surface thereof. Subsequently, the semiconductor dies (402a, 402b) may be singulated from the semiconductor wafer, whereupon the same resilient contact structures (430) can be used to effect interconnections between the semiconductor dies and other electronic components (such as wiring substrates, semiconductor packages, etc.). Using the all-metallic composite interconnection elements (430) of the present invention as the resilient contact structures, burn-in (792) can be performed at temperatures of at least 150 DEG C, and can be completed in less than 60 minutes.

Abstract translation: 在将模具（402a，402b）与半导体晶片分离（分离）之前，将弹性接触结构（430）直接安装在半导体管芯（402a，402b）上的接合焊盘（410）上。 这使得半导体管芯（402a，402b）能够通过用具有多个端子的电路板（710）等连接到半导体管芯（702,704）来实现（例如，测试和/或烧入）半导体管芯（402a，402b） （712）设置在其表面上。 随后，半导体管芯（402a，402b）可以从半导体晶片分离，于是可以使用相同的弹性接触结构（430）来实现半导体管芯和其它电子部件（例如布线基板，半导体封装， 等等。）。 使用本发明的全金属复合互连元件（430）作为弹性接触结构，老化（792）可以在至少150℃的温度下进行，并且可以在少于60分钟内完成。

公开(公告)号：WO1995014312A1

公开(公告)日：1995-05-26

申请号：PCT/US1994013051

申请日：1994-11-14

Applicant: BERG TECHNOLOGY, INC.

Inventor： BERG TECHNOLOGY, INC. ,  BELOPOLSKY, Yakov

IPC: H01R04/02

CPC classification number: H05K3/3426 ,  H01R4/028 ,  H05K2201/10325 ,  H05K2201/1084 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613

Abstract: An improved connector (10) for an electronic module (16) or the like includes a housing (22, 24) having a socket opening that is sized and configured to accept an electronic module, and a plurality of terminals mounted to the housing. Each of the terminals (26) has a foot portion (28) having a layer of non-solderable material coated on one side of the foot portion to prevent solder from adhering to that side. A capillary nest (54) is formed by a channel surface on the underside of the foot portion when the terminal is mounted on a conductor pad such that solder flows through the capillary nest under the influence of capillary forces from the side of the terminal having a non-solderable coating thereon to the other side for forming a solder joint on that other side. A ring (50) of non-solderable material is coated around a middle portion of the terminal to prevent solder from flowing to the electrical contact surfaces located above the ring. As a result, the connector terminals can be soldered to a printed circuit board or the like in a simple and inexpensive manner and without the formation of known solder defects.

Abstract translation: 用于电子模块（16）等的改进的连接器（10）包括具有插座开口的壳体（22,24），该插座开口的尺寸和构造适于接纳电子模块，以及安装到壳体的多个端子。 每个端子（26）具有足部（28），其具有涂覆在脚部的一侧上的不可焊接材料层，以防止焊料粘附到该侧。 当端子安装在导体焊盘上时，毛细管座（54）由底部的下侧上的通道表面形成，使得焊剂在毛细管力的影响下从具有 不可焊接的涂层到另一侧，用于在另一侧形成焊接接头。 围绕端子的中间部分涂覆不可焊接材料的环（50），以防止焊料流到位于环上方的电接触表面。 结果，可以以简单且廉价的方式将连接器端子焊接到印刷电路板等上，并且不形成已知的焊料缺陷。

公开(公告)号：WO1995009437A1

公开(公告)日：1995-04-06

申请号：PCT/US1994010439

申请日：1994-09-16

Applicant: OLIN CORPORATION

Inventor： OLIN CORPORATION ,  MAHULIKAR, Deepak ,  PARTHASARATHI, Arvind

IPC: H01L21/56

CPC classification number: H01L24/32 ,  H01L23/49579 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/48624 ,  H01L2224/48639 ,  H01L2224/48699 ,  H01L2224/48724 ,  H01L2224/48739 ,  H01L2224/48824 ,  H01L2224/48839 ,  H01L2224/73265 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K3/3426 ,  H05K2201/10689 ,  H05K2201/10909 ,  H05K2201/2081 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00

Abstract: There is disclosed a process for the assembly of an electronic package (30) in which the outer lead ends (14) of a leadframe (50) are solderable (38) to external circuitry (36) without the necessity of a tin or solder coat. An oxidation resistant layer (44) is deposited on the leadframe (50) prior to package (30) assembly. The oxidation resistant layer (44) is removed prior to outer lead (14) soldering (38) providing a clean, oxide free metallic surface (46) for soldering (38).

Abstract translation: 公开了一种用于组装电子封装（30）的方法，其中引线框架（50）的外部引线端（14）可焊接（38）到外部电路（36），而不需要锡或焊料涂层 。 在封装（30）组装之前，在引线框架（50）上沉积抗氧化层（44）。 在外引线（14）焊接（38）之前去除抗氧化层（44），提供用于焊接（38）的清洁的，无氧化物的金属表面（46）。

公开(公告)号：WO1991000619A1

公开(公告)日：1991-01-10

申请号：PCT/US1990003572

申请日：1990-06-22

Applicant: RAYCHEM CORPORATION

Inventor： RAYCHEM CORPORATION ,  CRAY, Seymour, R. ,  KRAJEWSKI, Nicholas, J.

IPC: H01L23/538

CPC classification number: H01L23/5385 ,  H01L23/5384 ,  H01L24/45 ,  H01L24/49 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/4943 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2225/06596 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01039 ,  H01L2924/01079 ,  H01L2924/14 ,  H05K2201/1059 ,  H05K2201/10825 ,  H05K2201/10909 ,  H05K2203/0495 ,  H01L2224/48 ,  H01L2924/00 ,  H01L2924/20757 ,  H01L2924/01204 ,  H01L2224/05599

Abstract: A method and apparatus for interconnecting electronic circuits using nearly pure soft annealed gold mechanically compressed within through-plated holes. The invention has its application in attaching integrated circuit dice (104) directly to circuit boards (110) by ball bonding gold wires (101) to the bonding pads of the integrated circuit dice in a substantially perpendicular relationship to the surfaces of the dice and inserting the gold leads into through-plated holes (111) of circuit boards (110) which provide an electrical and a mechanical connection once the leads are compressed within the through-plated holes. The present invention also finds its application in the interconnection of sandwiched circuit board assemblies where soft gold lead wires are inserted into axially aligned through-plated holes of the circuit boards and compressed so that the gold lead wires compress and buckle within the through-plated holes, forming an electrical connection between the circuit boards.

Abstract translation: 一种使用在纯通孔内机械压缩的几乎纯软的退火金的互连电子电路的方法和装置。 本发明的应用是将集成电路芯片（104）直接连接到电路板（110）上，通过将金线（101）以与芯片表面基本垂直的方式与集成电路晶片的接合焊盘接合并插入 一旦引线在通孔内被压缩，金会导致电路板（110）的通孔（111），其提供电和机械连接。 本发明还将其应用于夹层电路板组件的互连中，其中软金导线插入到电路板的轴向对齐的通孔中并被压缩，使得金引线在穿透孔内压缩和弯曲 在电路板之间形成电连接。

公开(公告)号：JP2018510507A

公开(公告)日：2018-04-12

申请号：JP2017544948

申请日：2016-02-25

Applicant: エプコス アクチエンゲゼルシャフト ,  EPCOS AG

Inventor： コイニ,マルクス ,  アウアー,クリストフ ,  コンラッド,ユルゲン ,  リンナー,フランツ ,  プフ,マルクス ,  シュタットローバー,モニカ ,  ビッペル,トーマス

IPC: H01G4/30 ,  H01G2/06 ,  H01G4/12 ,  H01G4/228 ,  H01G4/232

CPC classification number: H01G4/228 ,  H01G2/06 ,  H01G4/232 ,  H01G4/2325 ,  H01G4/30 ,  H01G4/38 ,  H05K1/181 ,  H05K3/3426 ,  H05K2201/10015 ,  H05K2201/10757 ,  H05K2201/10818 ,  H05K2201/10909 ,  Y02P70/613

Abstract: セラミック素子(2)用の電気接続用接点(5)を示す。この接続用接点(5)は、第1材料(M1)と、その上に配置されている第2材料(M2)とを有し、第1材料(M1)は導電性が大きく、第2材料(M2)は熱膨張係数が小さい。

公开(公告)号：JP5350962B2

公开(公告)日：2013-11-27

申请号：JP2009228371

申请日：2009-09-30

Applicant: 富士通株式会社 ,  富士通コンポーネント株式会社

Inventor： 浩晃 田村 ,  史彦 十倉 ,  進直 野村 ,  敏弘 草谷 ,  和宏 水上

IPC: H01R4/02 ,  G06F1/18 ,  H01R12/57

CPC classification number: H05K3/3426 ,  H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49582 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/181 ,  H05K2201/09136 ,  H05K2201/10189 ,  H05K2201/10689 ,  H05K2201/10787 ,  H05K2201/10909 ,  H05K2201/10946 ,  H05K2201/10984 ,  Y02P70/613 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: An electronic component includes: an electronic component body; and a lead secured to the electric component and including a projection portion defined by first and second inclined portions facing each other. The solder wettability of the first inclined portion is smaller than the solder wettability of the second inclined portion.