公开(公告)号：JP2002111040A

公开(公告)日：2002-04-12

申请号：JP2000286180

申请日：2000-09-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHO SHUNZAI

IPC: H01L27/146 ,  H01L31/10

Abstract: PROBLEM TO BE SOLVED: To provide a photodiode structure for reducing the leakage current of a junction section to approximately 1/10 as compared with a conventional photodiode device, and the manufacturing method of the photodiode structure. SOLUTION: The photodiode structure comprises a second-conductivity-type region 210 that is formed at a specific region from an isolation region 204 adjacent to a substrate 200, and a mask layer for covering at least a peripheral strip near the edge of the isolation region so that the doped second-conductivity- type region is exposed.

公开(公告)号：JP2002041156A

公开(公告)日：2002-02-08

申请号：JP2000212568

申请日：2000-07-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KIM C HARDY

IPC: G05F1/56

Abstract: PROBLEM TO BE SOLVED: To provide a voltage down converter which can be realized by on-chip whose high load performance is improved. SOLUTION: This voltage down converter is provided with a hysteresis generator for combining a hysteresis signal with a reference voltage and an output voltage feedback signal to be applied to a comparator. The hysteresis generator is connected to a control signal for preliminarily announcing when a high current load is activated. The hysteresis signal is switched to a first state before the high current load is activated, and switched over to a second state after the high current load is activated. In the first state, the hysteresis voltage is added to the reference voltage. In the second state, the hysteresis voltage is added to the voltage output feedback signal.

公开(公告)号：JP2001168189A

公开(公告)日：2001-06-22

申请号：JP34550499

申请日：1999-12-03

Applicant: UNITED MICROELECTRONICS CORP

Inventor： O SHIMEI

IPC: H01L23/522 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a dual damascene with a dielectric layer formed on a substrate equipped with a first conductive line and an air gap. SOLUTION: A method for forming a dual damascene structure has a step for forming a dielectric layer on the first conductive line, a step for forming a via-hole opening so as to expose the first conductive line in the dielectric material and the dielectric layer so as to expose the first conductive line, and a step for forming a second conductive line and a via-plug by filling the trench and the via-hole opening with a conductive material.

公开(公告)号：JP2001044385A

公开(公告)日：2001-02-16

申请号：JP21098599

申请日：1999-07-26

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  YEW TRI-RUNG

IPC: H01L21/26 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a DRAM capacitor dielectric film having superior dielectric constant. SOLUTION: After a ditantalum pentoxide dielectric film 104 is deposited on a surface of a polysilicon accumulating electrode 102, is the ditantalum pentoxide dielectric film is subjected to two-stage process, and first a remote oxygen plasma process or an UV-ray ozone process is carried out, and next a spike annealing process is carried out. Thus, when the ditantalum pentoxide dielectric film is subjected to two-stage process, the first stage remote oxygen plasma is emitted at relatively lower temperature, and also as the required time of a second stage spike annealing process is extremely short, a thermal history of a manufacture process of a dielectric film can be reduced.

公开(公告)号：JP2000349281A

公开(公告)日：2000-12-15

申请号：JP15531199

申请日：1999-06-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHEN CHIN-RAI ,  RIN TONII ,  CHOU JI-UEN

IPC: H01L29/78 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To lessen a parasitic capacitance between a gate and a drain and another parasitic capacitance between a gate and a source, by a method wherein a MOS transistor with a side slot is provided between a dielectric layer and the left side or right side of a conductive layer located under a metal silicide layer. SOLUTION: A substrate wafer 33, a drain 34, and a source 36 located apart from the drain 34 in a different region on a surface layer are formed on a substrate 31, and an insulating layer 38 is formed on the surface of the substrate 31 between the drain 34 and the source 36. The drain 34, source 36, and metal silicide layer 38 of the gate 40 are covered with a dielectric layer 50, and the dielectric layer 50 is made to function as an insulating layer outside a MOS transistor 29. The MOS transistor 29 is located so as to position two empty side slots 52 on lateral sides of the conductive layer 42 and between the conductive layer 42 and an upper part 44 below the dielectric layer 50 and the metal silicide layer 48.

公开(公告)号：JP2000340762A

公开(公告)日：2000-12-08

申请号：JP13983299

申请日：1999-05-20

Applicant: UNITED MICROELECTRONICS CORP

Inventor： KO KOKUTAI ,  YEW TRI-RUNG ,  RO KATETSU

IPC: H01L27/04 ,  H01L21/265 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing the storage node for a capacitor. SOLUTION: After an insulating layer 108 is formed on a substrate 100, and is subjected to an ion-implantation step. Then, the insulating layer is patterned to provide an opening 112 which is exposed as a part of the substrate on the insulating layer 108, and a patterned conductor layer 114 is so formed as to fill the opening on the insulating layer, forming a hemispherical Si particle layer on the conductor layer. The order, in which the ion-implantation step is performed, may be changed as required. In this case, the opening for exposing a part of the substrate is provided at the insulating layer, before being subjected to ion-implantation.

公开(公告)号：JP2000332197A

公开(公告)日：2000-11-30

申请号：JP13319599

申请日：1999-05-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SEN MEICHI ,  RIN SEITOKU

IPC: H01L27/04 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To reduce the size of a package and to simplify a packaging process. SOLUTION: The wafer level package is provided with a silicon chip 11 with an integrated circuit device 14, insulation layers 18a-18c for covering the integrated circuit device 14, a bonding pad 24 that is dispersively arranged along an edge 35 of the silicon chip 11 and further is electrically connected to the terminal of the integrated circuit device 14, a protection layer 30 for covering one portion of the insulation layer 18c and the bonding pad 24, a metal layer 34 that covers the exposed part of the bonding pad 24 and is extended to the edge 35, a packaging layer 36 that is provided on the protection layer 34, and a plurality of metal bumps 38 being provided on the metal layer 34.

公开(公告)号：JP2000332015A

公开(公告)日：2000-11-30

申请号：JP13164499

申请日：1999-05-12

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RYU SHIKEN ,  O KONCHI ,  SHA BUNEKI ,  KO MASUTAMI

IPC: H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To prevent flaking of a silicon-rich nitride(SRN) layer from a copper layer and the resulting diffusion of copper by causing dangling-bonded silicon within the SRN layer to react with the copper layer, to thereby form copper silicide between the SRN and copper layers. SOLUTION: A silicon rich nitride layer 212 is formed on a dielectric layer 202 by a plasma CVD method, using an evaporation gases, such as silane and ammonium. By adjusting the percentage of flow rate of silane to ammonium, the layer 212 results in containing more silicon component than nitrogen component. Since the layer 212 has a large number of Si-H dangling bonds therein, Si-H bonds react with copper, thereby forming a copper silicide layer 214 between the exposed copper layers 210b and 210c and the layer 212 and improving their adhesion. Therefore, the layer 212 will not exfoliate from copper due to stresses caused at its interface.

公开(公告)号：JP2000323691A

公开(公告)日：2000-11-24

申请号：JP12300999

申请日：1999-04-28

Applicant: UNITED MICROELECTRONICS CORP

Inventor： RIN SHIGYO ,  CHIN SHUKUREI ,  YO JOHO

IPC: H01L31/10 ,  H01L27/14 ,  H01L27/148

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor image sensor having an improved transmissivity for a blue-color light. SOLUTION: This semiconductor image sensor is provided with a bonding pad 302 formed on a semiconductor substrate 300. An oxide layer 304 is arranged on the semiconductor substrate 300 to cover the bonding pad 302. An SOG 306 is arranged on the oxide layer 304, and a silicon oxynitride layer 310 is arranged on the SOG 306, and then a color filter 312 is arranged thereon. Due to high transmissivity of the SOG 306 and the adoption of the silicon oxynitride layer 310, the transmissivity for blue-color light in the semiconductor image sensor can be improved.

公开(公告)号：JP2000315717A

公开(公告)日：2000-11-14

申请号：JP11707799

申请日：1999-04-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： TEI CHOGEN

IPC: H01L21/677 ,  H01L21/68

Abstract: PROBLEM TO BE SOLVED: To provide a wafer extruder, which prevents wafers from being broken or from being dually laminated, in a vertical wafer carrying system. SOLUTION: A vertical wafer carrying system is provided with a wedge type wafer extruder 130 on a wafer boat 120 for vertically carrying a plurality of wafers 110. The wafers 110 are put in the same slant direction during the time when the wafers 110 are vertically carried and the wedge type wafer extruder 130 is provided with a slant face for supporting the wafers 110.