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公开(公告)号：KR1020170089466A
公开(公告)日：2017-08-04
申请号：KR1020160009519
申请日：2016-01-26
Applicant: 한국전자통신연구원
Abstract: 본발명의실시예에따른궤환증폭기는입력단자로부터입력되는입력신호를증폭시켜출력단자로출력하는증폭회로부와, 상기입력단자와상기출력단자사이에직렬로연결된제1 고정저항과제2 고정저항을포함하는궤환회로부와, 서로다른레벨의제어신호에따라상기제1 고정저항의적용여부를결정하는신호레벨동작선택부와, 상기제어신호에따라상기제2 고정저항의적용여부를제어하는신호검출부와, 바이어스전압을생성하는바이어스회로부를포함하고, 상기제1 고정저항과상기제2 고정저항은상기제어신호에따라선택적으로적용한다.
Abstract translation: 根据本发明实施例的反馈放大器包括：放大器电路部分，用于放大从输入端子输入的输入信号并将放大的输入信号输出到输出端子;以及第一固定电阻任务2固定电阻器，串联连接在输入端子和输出端子之间 信号电平操作选择器，用于根据不同电平的控制信号确定是否施加第一固定电阻器，信号检测器，用于根据控制信号控制是否施加第二固定电阻器， 以及用于产生偏置电压的偏置电路，其中根据控制信号选择性地施加第一固定电阻器和第二固定电阻器。
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公开(公告)号：KR101616156B1
公开(公告)日：2016-04-27
申请号：KR1020120018591
申请日：2012-02-23
Applicant: 한국전자통신연구원
IPC: H01L29/812 , H01L21/338
Abstract: 본발명은질화물전자소자및 그제조방법에관한것으로서, 상세하게는갈륨(Gallium: Ga), 알루미늄(Aluminum: Al), 인듐(Indium: In) 등의 3족원소및 질소를포함하는 3족질화물(III-Nitride) 반도체전자소자에서사용되는반절연성질화갈륨(GaN)층의재성장기술(Epitaxially Lateral Over-Growth: ELOG)을통해다양한형태의질화물집적구조를동일기판위에구현할수 있는질화물전자소자및그 제조방법에관한것이다.
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公开(公告)号：KR1020160037747A
公开(公告)日：2016-04-06
申请号：KR1020150120212
申请日：2015-08-26
Applicant: 한국전자통신연구원
Abstract: 반도체채널저항의등가회로를구성하는방법은, 반도체채널저항의제 1 전극및 제 2 전극을정의하는단계, 상기제 1 전극및 상기제 2 전극사이에연결되는수동소자부를정의하는단계및 상기수동소자부내 상기적어도두 개의수동소자의파라미터값을각각결정하는단계를포함한다. 여기에서, 상기수동소자부는병렬연결된적어도두 개의수동소자를포함한다. 따라서, 주파수변화에도불구하고반도체채널저항의특성을정확히나타낼수 있다.
Abstract translation: 一种用于构造半导体沟道电阻器的等效电路的方法包括限定半导体沟道电阻器的第一电极和第二电极的步骤，限定连接在第一电极和第二电极之间的无源元件部分的步骤，以及 分别确定无源元件部分中的至少两个无源元件的参数值的步骤。 这里，无源元件部分包括并联连接的至少两个无源元件。 因此，即使频率变化，也能够准确地显示半导体通道电阻的特性。
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公开(公告)号：KR1020150086014A
公开(公告)日：2015-07-27
申请号：KR1020140006091
申请日：2014-01-17
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335 , H01L29/78
CPC classification number: H01L24/05 , H01L24/03 , H01L24/48 , H01L2224/0225 , H01L2224/03466 , H01L2224/03848 , H01L2224/0401 , H01L2224/04042 , H01L2224/05083 , H01L2224/05084 , H01L2224/05124 , H01L2224/05144 , H01L2224/05155 , H01L2224/05166 , H01L2224/05644 , H01L2224/48463 , H01L2924/00014 , H01L2924/10158 , H01L2924/1033 , H01L2924/1304 , H01L2924/13091 , H01L2924/1423 , H01L2924/201 , H01L2924/37001 , H01L2224/45099
Abstract: 본발명은 GaN 트랜지스터와그 제조방법에관한것으로, 와이어본딩또는후면비아홀공정에적합하도록소오스, 드레인및 게이트의본딩패드가장자리에오믹금속층을형성시키는것으로본딩패드구조를개선한것이다. 이에따라, GaN 트랜지스터제작시오믹금속을본딩패드의가장자리에형성함으로써본딩패드의금속층과 GaN 기판과의접착력을강화시켜와이어본딩또는후면비아홀공정시패드층이분리되는현상을최소화하고소자의신뢰성을향상시키는효과가있다.
Abstract translation: 本发明涉及GaN晶体管及其制造方法。 在栅极，漏极和源极的焊盘边缘上形成欧姆金属层，以进行引线接合或背面通孔工艺。 改善了焊盘。 因此，可以通过在制造GaN晶体管时在焊盘的边缘上形成欧姆金属来增强焊盘的金属层与GaN衬底之间的粘合。 因此，可以使引线接合或背面通孔工序中的焊盘层的分离最小化，并且可以提高器件的可靠性。
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公开(公告)号：KR1020140075946A
公开(公告)日：2014-06-20
申请号：KR1020120143702
申请日：2012-12-11
Applicant: 한국전자통신연구원
IPC: H01L29/778 , H01L21/335
CPC classification number: H01L29/778 , H01L29/402 , H01L29/42316 , H01L29/66431
Abstract: A high electron mobility transistor is provided. The transistor includes a source electrode and a drain electrode disposed on a substrate to be spaced apart; a T-shaped gate electrode disposed between the source electrode and the drain electrode on the substrate; and a plurality of insulating films interposed between the substrate and the T-shaped gate electrode. The plurality of insulating films is composed of a first insulating film, a second insulating film, and a third insulating film. The third insulating film is interposed between the substrate and the head part of the T-shaped gate electrode to be in contact with the leg part of the T-shaped gate electrode. The second insulating film is interposed between the substrate and the head part of the T-shaped gate electrode to be in contact with the third insulating film. The first insulating film and the third insulating film stacked in order are interposed between the substrate and the head part of the T-shaped gate electrode to be in contact with the second insulating film.
Abstract translation: 提供高电子迁移率晶体管。 晶体管包括设置在基板上的源电极和漏电极以被间隔开; 设置在基板上的源电极和漏电极之间的T字栅电极; 以及插入在所述基板和所述T形栅电极之间的多个绝缘膜。 多个绝缘膜由第一绝缘膜，第二绝缘膜和第三绝缘膜构成。 第三绝缘膜插入到基板和T形栅电极的头部之间，以与T形栅电极的腿部接触。 第二绝缘膜插入到基板和T形栅电极的头部之间以与第三绝缘膜接触。 按顺序堆叠的第一绝缘膜和第三绝缘膜介于基板和T形栅电极的头部之间以与第二绝缘膜接触。
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Patent Agency Ranking
公开(公告)号：KR1020140048026A
公开(公告)日：2014-04-23
申请号：KR1020130029769
申请日：2013-03-20
Applicant: 한국전자통신연구원
IPC: H01L21/3205 , H01L21/28 , H01L21/768
CPC classification number: H01L21/76898 , H01L21/76877 , H01L23/481 , H01L23/535
Abstract: A semiconductor device according to the concept of the present invention may include a substrate having a lower via hole; an epi layer which has an opening part for exposing the upper surface of the substrate; a semiconductor chip which is provided on the upper surface of the substrate and includes a first electrode, a second electrode, and a third electrode; an upper metal layer connected to the first electrode; a support plate which is arranged on the upper metal layer and has an upper via hole; an upper pad which is arranged on the support substrate and is extended to the inner part of the upper via hole; a lower pad which is arranged in the opening pad and is connected to the second electrode; and a lower metal layer which covers the lower surface of the substrate and is connected to the lower pad through the lower via hole.
Abstract translation: 根据本发明的概念的半导体器件可以包括具有下通孔的衬底; 外延层，其具有用于使基板的上表面露出的开口部; 半导体芯片，其设置在所述基板的上表面，并且包括第一电极，第二电极和第三电极; 连接到第一电极的上金属层; 支撑板，其设置在上金属层上并具有上通孔; 上垫，其布置在所述支撑基板上并延伸到所述上通孔的内部; 下垫，其布置在所述开口垫中并连接到所述第二电极; 以及覆盖基板的下表面并通过下通孔连接到下焊盘的下金属层。
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公开(公告)号：KR1020130066934A
公开(公告)日：2013-06-21
申请号：KR1020110133715
申请日：2011-12-13
Applicant: 한국전자통신연구원
IPC: H01L21/338 , H01L29/812
CPC classification number: H01L29/0649 , H01L21/28593 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7786
Abstract: PURPOSE: A semiconductor device including a step gate electrode and a manufacturing method thereof are provided to increase a breakdown voltage by using optical photoresist and two nitride layers. CONSTITUTION: A cap layer(211) is formed on a semiconductor substrate. An active area is formed by etching a part of the cap layer. A resist pattern is formed on the active area and the cap layer. A step gate electrode(225) is formed by depositing heat-resistant metal. An insulation layer(227) is deposited by removing a gate head pattern.
Abstract translation: 目的：提供包括步进栅电极及其制造方法的半导体器件，以通过使用光致抗蚀剂和两个氮化物层来增加击穿电压。 构成：在半导体衬底上形成覆盖层（211）。 通过蚀刻盖层的一部分形成有源区。 在有源区域和盖层上形成抗蚀剂图案。 通过沉积耐热金属形成步进栅电极（225）。 通过去除栅极头图案来沉积绝缘层（227）。
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公开(公告)号：KR1020120068599A
公开(公告)日：2012-06-27
申请号：KR1020100130291
申请日：2010-12-17
Applicant: 한국전자통신연구원
IPC: H01L21/336 , H01L29/78
CPC classification number: H01L29/7831 , H01L29/2003 , H01L29/404 , H01L29/42316 , H01L29/66462 , H01L29/66863 , H01L29/7787 , H01L29/812 , H01L29/7783
Abstract: PURPOSE: A field effect transistor and a manufacturing method thereof are provided to control an insulation film property of the lower side of an electric field electrode by controlling the thickness of an insulation film on the lower side of each electric field electrode in a field effect transistor. CONSTITUTION: A source electrode, a drain electrode, and a gate electrode are formed on the upper side of a semiconductor substrate(20). A multilayer electric field electrode pattern with a different exposure layer with an opening unit is formed by depositing and patterning a multilayer photosensitive film on the upper side of an insulation film(27). An insulation film with a different step is formed by an insulation film etching process using an electric field electrode pattern as an etch mask. An electric field electrode(30a,30b,30c) is formed on the upper side of the insulation film by lifting off a metal layer after the metal layer is deposited by using the electric field pattern.
Abstract translation: 目的：提供场效应晶体管及其制造方法，以通过控制场效应晶体管中每个电场电极下侧的绝缘膜的厚度来控制电场电极的下侧的绝缘膜性质 。 构成：在半导体衬底（20）的上侧形成源电极，漏电极和栅电极。 通过在绝缘膜（27）的上侧上沉积和图案化多层感光膜，形成具有开口单元的不同曝光层的多层电场电极图案。 通过使用电场电极图案作为蚀刻掩模的绝缘膜蚀刻工艺形成具有不同台阶的绝缘膜。 通过使用电场图案沉积金属层之后，通过剥离金属层，在绝缘膜的上侧形成电场电极（30a，30b，30c）。
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公开(公告)号：KR1020120066362A
公开(公告)日：2012-06-22
申请号：KR1020100127661
申请日：2010-12-14
Applicant: 한국전자통신연구원
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/42376 , H01L29/2003 , H01L29/40 , H01L29/402 , H01L29/42316 , H01L29/66462 , H01L29/7787 , H01L29/812
Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to improve a high voltage property of the semiconductor device by increasing a breakdown voltage. CONSTITUTION: A source electrode(210) is separated from a drain electrode(220) on a substrate(200). An insulation layer(230) is formed on the substrate, the source electrode, and the drain electrode. A field plate electrode(240) is formed on the insulation layer. A gate electrode(250) is contacted with the field plate electrode. The gate electrode includes a first support unit(251), a second support unit(252), and a head unit(253).
Abstract translation: 目的：提供半导体器件及其制造方法，以通过增加击穿电压来提高半导体器件的高电压特性。 构成：源电极（210）与衬底（200）上的漏电极（220）分离。 在基板，源电极和漏电极上形成绝缘层（230）。 在绝缘层上形成场板电极（240）。 栅电极（250）与场板电极接触。 栅电极包括第一支撑单元（251），第二支撑单元（252）和头单元（253）。
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公开(公告)号：KR1020120062346A
公开(公告)日：2012-06-14
申请号：KR1020100123566
申请日：2010-12-06
Applicant: 한국전자통신연구원
IPC: H01L21/8252 , H01L29/423 , H01L29/66 , H01L29/778 , H01L27/06
CPC classification number: H01L29/7783 , H01L21/8252 , H01L27/0605 , H01L29/42316 , H01L29/66462
Abstract: PURPOSE: A manufacturing method of a high frequency device structure is provided to reduce initial reaction energy with a substrate material while diffusing Pt/Pd in a thermal process, thereby stably manufacturing a normally-off type high frequency device. CONSTITUTION: A Schottky barrier layer, an etch-stop layer(106), an ohmic layer(107), and an ohmic electrode are formed on a substrate. A first recess is formed in order to expose a part of the etch-stop layer. A second recess is formed in order to expose a part of the Schottky barrier slayer after forming a gate pattern on the first recess. A gate electrode(115) is formed by depositing a heat resistant metal film after forming a super lattice film by alternately depositing Pt and Pd on the second recess and the gate pattern.
Abstract translation: 目的：提供一种高频器件结构的制造方法，以便在热处理中扩散Pt / Pd的同时降低与衬底材料的初始反应能量，从而稳定地制造常闭型高频器件。 构成：在衬底上形成肖特基势垒层，蚀刻停止层（106），欧姆层（107）和欧姆电极。 形成第一凹部以暴露部分蚀刻停止层。 形成第二凹部以便在第一凹部上形成栅极图案之后暴露一部分肖特基势垒屏障。 通过在第二凹部和栅极图案之间交替沉积Pt和Pd，在形成超晶格膜之后沉积耐热金属膜来形成栅电极（115）。
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