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129 records (took 0.024 seconds)

    101.
    发明专利
    未知

    公开(公告)号：ITTO20010529D0

    公开(公告)日：2001-06-01

    申请号：ITTO20010529

    申请日：2001-06-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  ZANARDI STEFANO ,  PICCA MASSIMILIANO ,  RAVASIO ROBERTO

    IPC: G06F11/10 ,  G06F12/00

    Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

    102.
    发明专利
    未知

    公开(公告)号：ITTO990994A1

    公开(公告)日：2001-05-16

    申请号：ITTO990994

    申请日：1999-11-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

    IPC: G11C5/14 ,  G11C11/56 ,  G11C16/30

    Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

    103.
    发明专利
    未知

    公开(公告)号：ITMI990722A1

    公开(公告)日：2000-10-09

    申请号：ITMI990722

    申请日：1999-04-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CRIPPA LUCA

    IPC: G05F3/30

    Abstract: Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.

    106.
    发明专利
    未知

    公开(公告)号：DE602006008738D1

    公开(公告)日：2009-10-08

    申请号：DE602006008738

    申请日：2006-05-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: G11C8/08 ,  G11C16/12

    Abstract: A circuit is disclosed. The circuit comprises a first input terminal (INA1), a second input terminal (INA2) and an output terminal (OUT). The circuit further includes a first circuital branch (610) connected between the first input terminal and the output terminal, and a second circuital branch (620) connected between the second input terminal and the output terminal. The first circuital branch is selectively activatable for coupling the first input terminal with the output terminal, and the second circuital branch is selectively activatable for coupling the second input terminal with the output terminal. The first and second circuital branches comprise each at least one electronic device having at least a first and a second device terminals. Said at least one electronic device is designed to guarantee the capability of sustaining voltage differences across at least the first and second device terminals thereof that are up-limited in absolute value by a first predetermined maximum value lower than the maximum of absolute values of voltage differences between the output terminal and the first input terminal, and between the output terminal and the second input terminal, respectively.

    107.
    发明专利
    未知

    公开(公告)号：DE60139670D1

    公开(公告)日：2009-10-08

    申请号：DE60139670

    申请日：2001-04-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GREGORI STEFANO ,  MICHELONI RINO ,  PIERIN ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO

    IPC: G11C16/02 ,  G11C16/12 ,  G11C11/56

    Abstract: The method involves applying in succession, to a control terminal of the memory cell, at least two programming pulse trains (F1,F2) with pulse amplitude increasing in staircase fashion. The amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Transition from the first programming pulse to train to the second is made when the memory cell has a threshold voltage with a pre-set relation with a reference value.

    108.
    发明专利
    未知

    公开(公告)号：DE602006006029D1

    公开(公告)日：2009-05-14

    申请号：DE602006006029

    申请日：2006-04-12

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: G11C16/24 ,  G11C7/12 ,  G11C8/10

    Abstract: A column decoding system (140,150) for selectively biasing bit lines (BLij) of a non-volatile memory device (100) is disclosed. The bit lines are logically grouped into at least one packet (PBL). For each packet, the column decoding system includes a plurality of selection paths each one for applying a biasing voltage to a corresponding bit line, each path including a plurality of series-connected selection transistors (Mi,Mij,Pij) each one having a threshold voltage, and selection means for selecting a path (M1,M11,P11) corresponding to a selected bit line (BL11), the selection means including means for biasing at least one transistor (P12) in each non-selected path (M1,M12,P12) to an open condition to have the corresponding non-selected bit line (BL12) floating; the selection means further includes means for biasing at least one other transistor (M12) in each non-selected path to a drop condition to introduce a voltage drop in the non-selected path higher than the threshold voltage of said one transistor (P12) in absolute value.

    110.
    发明专利
    未知

    公开(公告)号：DE60129786D1

    公开(公告)日：2007-09-20

    申请号：DE60129786

    申请日：2001-01-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  MICHELONI RINO

    IPC: G11C11/56 ,  G11C7/06 ,  G11C16/06 ,  G11C16/02 ,  G11C16/26

    Abstract: The method for reading a memory cell is based upon integration in time of the current supplied to the memory cell (36) by a capacitive element (22, 23). The capacitive element (22, 23) is initially charged and then discharged linearly in a preset time, while the memory cell (36) is biased at a constant voltage. In a first operating mode, initially a first capacitor (22) and a second capacitor (23) are respectively charged to a first charge value and to a second charge value. The second capacitor (23) is discharged through the memory cell (36) at a constant current in a preset time; the first charge is shared between the first capacitor (22) and the second capacitor (23); and then the shared charge is measured.

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