公开(公告)号：US20240147617A1

公开(公告)日：2024-05-02

申请号：US18548458

申请日：2022-03-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takayoshi NIRENGI ,  Akihiro OISHI ,  Tsutomu AISAKA ,  Daisuke MATSUSHITA ,  Jumpei IWANAGA ,  Tadashi TOJO

IPC: H05K1/09 ,  H05K3/46

CPC classification number: H05K1/09 ,  H05K3/46 ,  H05K2201/0753 ,  H05K2201/095

Abstract: A wiring body disposed above a substrate including a conductor including: a via electrode provided in a via hole formed in an insulating layer above the substrate and connected to the conductor through the via hole; and wiring provided above the substrate with the insulating layer interposed therebetween. A lower layer included in the via electrode and located above the insulating layer and a lower layer included in the wiring include the same material.

公开(公告)号：US11842958B2

公开(公告)日：2023-12-12

申请号：US17697937

申请日：2022-03-18

Applicant: Chun-Ming Lin

Inventor： Chun-Ming Lin

IPC: H05K1/09 ,  H05K1/11 ,  H01L23/498 ,  C25D7/12 ,  H01L21/48 ,  C25D3/38 ,  H05K1/18

CPC classification number: H01L23/49866 ,  C25D3/38 ,  C25D7/12 ,  H01L21/4857 ,  H01L23/49822 ,  H01L23/49827 ,  H05K1/09 ,  H05K1/112 ,  H05K1/18 ,  H05K2201/0332 ,  H05K2201/0364 ,  H05K2201/095 ,  H05K2201/09509

Abstract: The present disclosure provides a multilayer wiring structure, including a plurality of dielectric layers, a plurality of conductive wiring layers interleaved with the plurality of dielectric layers, wherein the plurality of conductive wiring layers includes copper-phosphorous alloys (such as Cu3P).

公开(公告)号：US20230369192A1

公开(公告)日：2023-11-16

申请号：US18226652

申请日：2023-07-26

Applicant: Intel Corporation

Inventor： Jonathan ROSCH ,  Wei-Lun JEN ,  Cheng XU ,  Liwei CHENG ,  Andrew BROWN ,  Yikang DENG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49827 ,  H05K1/111 ,  H01L21/486 ,  H05K1/115 ,  H01L23/49822 ,  H05K2201/09727 ,  H05K1/025 ,  H05K2201/09736 ,  H05K2201/09827 ,  H05K1/18 ,  H05K2201/095

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a semiconductor package. A package substrate includes a conductive layer in a dielectric, a first trace and a first via pad of the conductive layer having a first thickness, and a second trace and a second via pad of the conductive layer having a second thickness. The second thickness of second trace and second via pad may be greater than the first thickness of the first trace and first via pad. The dielectric may include a first dielectric thickness and a second dielectric thickness, where the second dielectric thickness may be less than the first dielectric thickness. The package substrate may include a third via having a third thickness on the first via pad, and a fourth via having a fourth thickness on the second via pad, wherein the third thickness is greater than the fourth thickness.

公开(公告)号：US20180368254A1

公开(公告)日：2018-12-20

申请号：US16109915

申请日：2018-08-23

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Toshiro ADACHI

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K1/03 ,  H05K3/46 ,  H05K3/00 ,  H05K3/40

CPC classification number: H05K1/0271 ,  H05K1/0313 ,  H05K1/092 ,  H05K1/115 ,  H05K3/0011 ,  H05K3/4038 ,  H05K3/46 ,  H05K3/4644 ,  H05K2201/068 ,  H05K2201/095

Abstract: A resin substrate includes a first portion including a plurality of resin sheets provided at one end in a stacking direction and a second portion including a plurality of resin sheets provided at the other end in the stacking direction. The thickness of the plurality of resin sheets is the same or substantially the same as the thickness of the first portion and the second portion. The density of planar conductor patterns of the first portion with respect to the volume of the first portion is lower than the density of planar conductor patterns of the second portion with respect to the volume of the second portion. The average of the diameters of the first interlayer connection conductor provided in the first portion is greater than the average of the diameters of the second interlayer connection conductor provided in the second portion.

公开(公告)号：US20170318669A1

公开(公告)日：2017-11-02

申请号：US15649830

申请日：2017-07-14

Applicant: Intel Corporation

Inventor： Kristof Darmawikarta ,  Daniel Sobieski ,  Kyu Oh Lee ,  Sri Ranga Sai Boyapati

IPC: H05K1/02 ,  H05K3/00 ,  H05K1/11 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0298 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/113 ,  H05K3/0041 ,  H05K3/181 ,  H05K3/188 ,  H05K3/4038 ,  H05K3/422 ,  H05K3/429 ,  H05K3/4644 ,  H05K2201/09218 ,  H05K2201/09372 ,  H05K2201/095 ,  H05K2201/096 ,  H05K2201/09654 ,  H05K2203/0548

Abstract: Some example forms relate to an electronic package. The electronic package includes a first dielectric layer that includes an electrical trace formed on a surface of the first dielectric layer and a second dielectric layer on the surface of the first dielectric layer. The second dielectric layer includes an opening. The electrical trace is within the opening. The electronic package includes an electrical interconnect that fills the opening and extends above an upper surface of the second dielectric layer such that the electrically interconnect is electrically connected to the electrical trace on the first dielectric layer.

公开(公告)号：US09769921B2

公开(公告)日：2017-09-19

申请号：US14732309

申请日：2015-06-05

Applicant: Tyco Electronics AMP Korea Ltd

Inventor： Yang Yoon Choi ,  Ok Ky Beak

IPC: H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K3/06 ,  H05K3/46 ,  H05K3/42 ,  C25D5/02 ,  C23C18/16 ,  C23C18/54 ,  H05K3/38 ,  H05K3/00

CPC classification number: H05K1/0298 ,  C23C18/1637 ,  C23C18/1653 ,  C23C18/54 ,  C25D5/02 ,  H05K1/0206 ,  H05K1/0251 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/06 ,  H05K3/386 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/462 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0323 ,  H05K2201/095 ,  H05K2203/072 ,  H05K2203/0723 ,  H05K2203/073 ,  H05K2203/1476

Abstract: A printed circuit board has a double-sided substrate with an insulation layer, a bonding member, a base layer of an aluminum material, and a circuit pattern; a second insulation layer; a second bonding member; a second base layer; a through hole; a zinc substitution layer; a plating layer; and a second circuit pattern.

公开(公告)号：US09763327B2

公开(公告)日：2017-09-12

申请号：US14834180

申请日：2015-08-24

Applicant: Multek Technologies Ltd.

Inventor： Kwan Pen ,  Pui Yin Yu

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H05K3/00 ,  H05K3/06 ,  H05K3/18

CPC classification number: H05K1/115 ,  H05K1/0216 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/0058 ,  H05K3/06 ,  H05K3/181 ,  H05K3/188 ,  H05K3/42 ,  H05K3/422 ,  H05K3/424 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4638 ,  H05K2201/095 ,  H05K2201/09545 ,  H05K2201/09554 ,  H05K2201/10303

Abstract: A selective segment via plating process for manufacturing a circuit board selectively interconnects inner conductive layers as separate segments within the same via. Plating resist is plugged into an inner core through hole and then stripped off after an electroless plating process. Stripping of the electroless plating on the plating resist results in a plating discontinuity on the via wall. In a subsequent electroplating process, the inner core layer can not be plated due to the plating discontinuity. The resulting circuit board structure has separate electrically interconnected segments within the via.

公开(公告)号：US20170156208A1

公开(公告)日：2017-06-01

申请号：US15431781

申请日：2017-02-14

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H01L23/00 ,  H01L23/498 ,  H05K1/18 ,  H05K1/05

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US09609749B2

公开(公告)日：2017-03-28

申请号：US14860718

申请日：2015-09-22

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US20170019998A1

公开(公告)日：2017-01-19

申请号：US14801422

申请日：2015-07-16

Applicant: Delphi Technologies, Inc.

Inventor： Rodrigo Franco

IPC: H05K1/14 ,  H05K1/11 ,  H05K3/40 ,  H05K3/36 ,  H05K3/42 ,  H05K1/18 ,  H05K3/32

CPC classification number: H05K1/144 ,  H05K1/111 ,  H05K1/115 ,  H05K1/14 ,  H05K1/141 ,  H05K1/145 ,  H05K1/181 ,  H05K1/183 ,  H05K3/32 ,  H05K3/3442 ,  H05K3/36 ,  H05K3/4007 ,  H05K3/429 ,  H05K2201/045 ,  H05K2201/09036 ,  H05K2201/09181 ,  H05K2201/095 ,  H05K2201/10166 ,  H05K2201/10727

Abstract: The circuit board assembly includes a first circuit board having a first plurality of electronic components attached to a major surface of the first circuit board. The first plurality of electronic components is electrically interconnected to a first plurality of conductive pads defined on the major surface of the first circuit board. A second circuit board has a second plurality of electronic components attached to a first major surface of the second circuit board. The second plurality of electronic components is electrically interconnected to a second plurality of conductive pads defined on a second major surface of the second circuit board. The first and second circuit board are attached by coupling the first and second plurality of conductive pads. A portion of the first plurality of electronic components on the first circuit board are disposed within a cavity defined by the second major surface of the second circuit board.

Abstract translation: 电路板组件包括具有附接到第一电路板的主表面的第一多个电子部件的第一电路板。 第一组多个电子部件电连接到限定在第一电路板的主表面上的第一多个导电焊盘。 第二电路板具有附接到第二电路板的第一主表面的第二多个电子部件。 所述第二多个电子部件电连接到限定在所述第二电路板的第二主表面上的第二多个导电焊盘。 第一和第二电路板通过联接第一和第二多个导电焊盘而附接。 第一电路板上的第一多个电子部件的一部分设置在由第二电路板的第二主表面限定的空腔内。