公开(公告)号：EP0303485A2

公开(公告)日：1989-02-15

申请号：EP88307441.1

申请日：1988-08-11

Applicant: BICC Public Limited Company

Inventor： Lawrence, Howard

IPC: H05K3/32 ,  H05K1/00 ,  H05K3/40

CPC classification number: H05K3/4046 ,  H05K1/118 ,  H05K3/0064 ,  H05K3/306 ,  H05K3/326 ,  H05K3/4611 ,  H05K2201/091 ,  H05K2201/09609 ,  H05K2201/10303 ,  H05K2201/1059 ,  H05K2201/2009

Abstract: A circuit board in which the patterns of electrically conductive strips and/or pads can be of either standard or non-standard form and which can be designed and assembled by a user comprises a rigid electrically insulating board 1 having a multiplicity of holes 2 through the board arranged in a pattern of rows and columns and, secured to one major surface of the board, a separately formed flexible sheet 4 of electrically insulating material carrying on the surface of the sheet remote from the board a pattern of electrically conductive strips and/or pads 8 which overlies holes in the board. The strips and/or pads 8 are of such an electrically conductive material and of such a thickness that, when a pin C is urged through an electrically conductive strip or pad and the underlying flexible sheet 4 into an underlying hole 2 in the board, electrically conductive material pierced by the pin will effect an electrical contact with the pin passing through the material.

Abstract translation: 其中导电带和/或垫的图案可以是标准或非标准形式并且可以由用户设计和组装的电路板包括刚性电绝缘板1，其具有穿过 板被布置成行和列的图案并且固定到板的一个主表面上，单独形成的电绝缘材料的柔性片4在片的远离板的表面上承载导电条的图案和/或 覆盖在电路板上的孔的焊盘8。 带和/或垫8是这样的导电材料，并且具有这样的厚度，以致当针C被推动穿过导电条或垫并且下面的柔性片4进入板中的下面的孔2时， 由销刺穿的导电材料将实现与穿过材料的销的电接触。

公开(公告)号：EP0249688A3

公开(公告)日：1988-05-04

申请号：EP87103898

申请日：1987-03-17

Applicant: International Business Machines Corporation

Inventor： Hitchcock, Robert Brewster ,  Kellerman, Eduardo ,  Koons, John Paul

IPC: H05K01/00

CPC classification number: H05K1/115 ,  H05K1/0289 ,  H05K2201/09236 ,  H05K2201/09609

Abstract: A printed circuit board (20) for electric circuits is formed of plural layers of electrical conductors (22, 24, 26) and includes through holes (36) and vias (38) arranged in a regular pattern along points of a grid laid out along othorgonal axes of a Cartesian coordinate system. Conductors (32, 34) of a layer (22, 24) are grouped together as multiple-conductor channels (44, 46) which are routed among the through holes (36) and the vias (38) to make electrical connections among the electrical components. An additional via (48) can be entered in a central portion of a grid cell by rerouting conductors of channels in the cell through arcuate segments, thereby permitting connection between conductors of channels on different layers while preserving the original grid pattern of through holes and vias.

公开(公告)号：EP0180183A3

公开(公告)日：1987-09-23

申请号：EP85113697

申请日：1985-10-28

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Igarashi, Yutaka ,  Hiraoka, Masaru

IPC: H05K03/46

CPC classification number: H05K1/116 ,  H05K1/0287 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09454 ,  H05K2201/09609 ,  H05K2201/0969 ,  H05K2201/09718 ,  H05K2201/09945 ,  H05K2201/10689

Abstract: A multilayer printed wiring board comprises at least one layer with interlayer connection pattern (200, 300) at the basic grids. The interlayer connection pattern (200, 300) has a clearance (62, 204, 304) when a small diameter through hole (60B) is formed and has a land part (63, 205, 303) contacted to the through hole wall (61A) when a large diameter through hole (60A) is formed. In order to obtain interlayer connection or non-connection, the diameter of a through hole is varied.

公开(公告)号：EP0236830A2

公开(公告)日：1987-09-16

申请号：EP87102549.0

申请日：1987-02-23

Applicant: CIRCUITGRAPH, S.L.

Inventor： Melero, Pedro Valenciano

IPC: H05K1/02

CPC classification number: H05K3/326 ,  H05K1/119 ,  H05K2201/09609 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/1059

Abstract: Eine Grundplatte (1) für elektrische Stromkreise besteht aus einem isolierenden, mit Durchgangslöchern (2) versehenen Schicht­körper. Damit die elektrischen Stromkreise einfacher und schneller hergestellt werden können, sind die Durchgangslöcher (2) kegelstumpfförmig, wobei der größere Durchmesser des Kegel­stumpfs größer und der kleinere Durchmesser des Kegelstumpfs kleiner ist als der Durchmesser der Anschlußteile der zu verbin­denden elektrischen Bauteile (Fig. 2).

Abstract translation: 用于电路的基板（1）由设有穿孔（2）的绝缘层状体构成。 为了使电路可以更加简单和快速地制造，穿孔（2）是截头圆锥形的，截头锥体的较大直径较大，截头圆锥体的直径小于直径 要连接的电气元件的连接部分（图2）。

公开(公告)号：EP0166289A2

公开(公告)日：1986-01-02

申请号：EP85107130.8

申请日：1985-06-11

Applicant: International Business Machines Corporation

Inventor： Kraus, Charles John ,  Stoller, Herbert Ivan ,  Wu, Leon Li-Heng

IPC: H05K1/00 ,  H01L23/52

CPC classification number: H01L23/5383 ,  H01L2224/16225 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/4629 ,  H05K2201/09609

Abstract: The wiring nets on a module are divided into two groups of planes, i.e., an upper group (5) in which wiring is placed along "north-south" and "east-west" directions and a lower group (6) in which wiring is placed along diagonal directions. All vias (R-vias) for connecting to the wiring pass through the upper group of planes but only half of the vias (D-vias) pass through the lower group of planes. Thus the spacing between the vias of the lower group of planes is greater than the spacing between the upper vias, allowing more lines per wiring channel in the lower group of planes.

公开(公告)号：EP0145549A3

公开(公告)日：1985-07-10

申请号：EP84402266

申请日：1984-11-09

Applicant: THOMSON-CSF

Inventor： Brault, Roland

IPC: H05K01/00

CPC classification number: H05K1/112 ,  H05K1/0295 ,  H05K1/0298 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09954 ,  H05K2201/10689

公开(公告)号：EP0130430A2

公开(公告)日：1985-01-09

申请号：EP84106836.4

申请日：1984-06-15

Applicant: International Business Machines Corporation

Inventor： Willie, Goff, Jr.

IPC: H05K3/46 ,  H05K3/08

CPC classification number: H05K3/08 ,  H05K1/09 ,  H05K3/325 ,  H05K3/368 ,  H05K2201/0323 ,  H05K2201/09609 ,  H05K2201/10378 ,  Y10T29/49004 ,  Y10T29/49126

Abstract: By use of an electroerosion technique a plurality of conductive lines are isolated out of an electrically conductive layer supported on an isolating substrate of a sheet (1) having holes in a distinct pattern. Several sheets (1) are superimposed in different planes and are alternately mixed with inerplane spacer-connector layers (24) between a terminal block (32) and a pressing guide block (33). The interplane spacer-connector layer (24) contains connectors (26) with contact areas (27, 28) interconnected with each other and make contact with isolated zones in different superimposed planes of sheets (1). The terminal block (32) is provided with sockets (35) for holding the terminals of circuit components of the to-be-developed electrical circuit.

公开(公告)号：EP0086961A2

公开(公告)日：1983-08-31

申请号：EP83100521.0

申请日：1983-01-21

Applicant: MUPAC CORPORATION

Inventor： Leary, Burton ,  Silverio, Shaun

IPC: H05K3/46 ,  H01R23/72

CPC classification number: H05K3/4641 ,  H05K1/0231 ,  H05K1/0287 ,  H05K1/162 ,  H05K3/222 ,  H05K2201/0191 ,  H05K2201/09309 ,  H05K2201/09609 ,  H05K2201/10287 ,  H05K2201/10333

Abstract: A panel board has a first voltage layer sandwiched between two ground layers at a close spacing to produce a large distributed capacitance; the two ground layers are connected by plated-through conductive holes spaced regularly across the board; a second (exposed) voltage layer is connected by regularly spaced plated-through holes to the first voltage layer, increasing the current carrying capacity of, and reducing the resistance across, the board; the plated-through holes are arranged in rows and columns in a pattern permitting the mounting of decoupling capacitors, at any point on the board, in a position parallel to the rows or parallel to the columns; and a socket terminal can be electrically connected directly to the exposed voltage layer or to the exposed ground layer using a ring connector.

公开(公告)号：EP3389347A1

公开(公告)日：2018-10-17

申请号：EP18166917.7

申请日：2018-04-12

Applicant: Pegatron Corporation

Inventor： YANG, Ching Ou ,  CHU, Cheng-Hui

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0263 ,  H05K1/0265 ,  H05K1/114 ,  H05K1/116 ,  H05K2201/09254 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09409 ,  H05K2201/09427 ,  H05K2201/09463 ,  H05K2201/09609 ,  H05K2201/09618 ,  H05K2201/0969 ,  H05K2201/09709 ,  H05K2201/0979

Abstract: A power signal transmission structure and a design method are provided. The power supply signal transmission structure is adapted for a circuit board having a first surface and a second surface opposite to the first surface, and the power signal transmission structure includes a first power electrode, a second power electrode, and a plurality of vias. The first power electrode is disposed on the first surface and has a plurality of power pad regions for receiving a power signal. The second power electrode is disposed on the second surface. The vias penetrate the circuit board to electrically connect the first power electrode and the second power electrode. The vias are arranged in accordance with the current direction of the power signal to balance the current received by the vias.

公开(公告)号：EP2829163B1

公开(公告)日：2017-08-09

申请号：EP13711574.7

申请日：2013-03-19

Applicant: Giesecke & Devrient GmbH

Inventor： BALDISCHWEILER, Michael ,  BOHN, Carsten

IPC: H05K1/11 ,  H05K3/40 ,  G06K19/077 ,  H05K1/09 ,  H05K1/16 ,  H05K3/12 ,  H05K3/00

CPC classification number: H05K1/116 ,  G06K19/0772 ,  G06K19/07754 ,  H05K1/092 ,  H05K1/165 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/1216 ,  H05K3/1233 ,  H05K3/4069 ,  H05K2201/0266 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/09609 ,  H05K2201/09709 ,  H05K2201/0979 ,  H05K2201/09854 ,  H05K2201/10098 ,  H05K2203/1453