公开(公告)号：WO1993026144A1

公开(公告)日：1993-12-23

申请号：PCT/CH1993000147

申请日：1993-06-10

Applicant: DYCONEX PATENTE AG ,  SCHMIDT, Walter ,  MARTINELLI, Marco

Inventor： DYCONEX PATENTE AG

IPC: H05K03/40

CPC classification number: H05K3/4084 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572

Abstract: The process for producing subsequently contactable contact points between two conductive track planes on a circuit substrate separated by an electrically insulating layer makes it possible to produce, for example, a basic conductor pattern which can subsequently be easily adapted to requirements. By laying windows in the conductive track planes out in such a way that, when the electrically insulating layer is subsequently through-etched due to under-etching, rod-like parts connected to the aperture periphery are revealed between or in the apertures which can be brought into contact with electrically conductive parts of the other conductive track plane, these conductive tracks can be electrically interconnected by mechanical bending.

公开(公告)号：WO1987004317A1

公开(公告)日：1987-07-16

申请号：PCT/US1986002758

申请日：1986-12-09

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  BROWN, Vernon, L.

IPC: H05K03/34

CPC classification number: H04M1/0262 ,  H01M2/1022 ,  H04B1/3883 ,  H05K1/0215 ,  H05K1/0237 ,  H05K1/144 ,  H05K3/0061 ,  H05K3/341 ,  H05K3/4038 ,  H05K3/4084 ,  H05K3/44 ,  H05K5/0086 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/0382 ,  H05K2201/09054 ,  H05K2201/09554 ,  H05K2201/10969 ,  Y02P70/613

Abstract: A unique housing (104 and 600) of a portable radio transceiver (100) that takes advantage of the heat sinking, electrical shielding and structural characteristics of a battery. The unique electronic circuitry housing (104 and 600) includes a battery as an integral structural element thereof. In one illustrated housing (104), a stick battery (210) is attached to the side of a transmitter printed circuit panel (213). A logic printed circuit panel (212) and a receiver printed circuit panel (214) are positioned above and below the transmitter printed circuit panel (213), respectively, and are held together by interlocking side rails (206, 207). In a second illustrated housing (600), a flat battery (602) is attached to the sides of a first U-shaped printed circuit panel (604). A second U-shaped printed circuit panel (606) is positioned between the battery and the first panel (604). Heat dissipated by the electrical components on the second panel (606) is conducted away by the flat battery (602). The electronic circuitry housing of the present invention may be advantageously utilized in a variety of applications where electronic circuitry is operated from a battery.

Abstract translation: 便携式无线电收发器（100）的独特外壳（104和600），其利用电池的散热，电屏蔽和结构特性。 独特的电子电路壳体（104和600）包括作为其整体结构元件的电池。 在一个示出的壳体（104）中，粘贴电池（210）附接到发射器印刷电路板（213）的侧面。 逻辑印刷电路板（212）和接收器印刷电路板（214）分别位于发射机印刷电路板（213）的上方和下方，并通过互锁的侧轨（206,207）保持在一起。 在第二示出的壳体（600）中，平坦电池（602）附接到第一U形印刷电路板（604）的侧面。 第二U形印刷电路板（606）位于电池和第一面板（604）之间。 由第二面板（606）上的电气部件耗散的热量由扁平电池（602）导出。 本发明的电子电路外壳可有利地用于电池从电池操作的各种应用中。

公开(公告)号：EP1520454B1

公开(公告)日：2012-01-25

申请号：EP03762158.8

申请日：2003-06-27

Applicant: PPG Industries Ohio, Inc.

Inventor： WANG, Alan E. ,  OLSON, Kevin C. ,  DI STEFANO, Thomas H.

IPC: H05K3/44 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09554 ,  H05K2201/10446 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A circuit board layer (2) in accordance with the present invention includes a conductive sheet (4) sandwiched between an insulating top layer (10) and an insulating bottom layer (14). The top and bottom layers (10) and (14) and the conductive sheet (4) define the circuit board layer (2) having an edge that includes an edge (20) of the conductive sheet (4). An insulating edge layer (18) covers substantially all of the edge (20) of the conductive sheet (4).

公开(公告)号：EP1491078B1

公开(公告)日：2010-06-23

申请号：EP03746044.1

申请日：2003-03-21

Applicant: Intel Corporation

Inventor： COOMER, Boyd ,  WALK, Michael

IPC: H05K3/46 ,  H05K3/44

CPC classification number: H01L21/4857 ,  H05K3/107 ,  H05K3/386 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K2201/0195 ,  H05K2201/09554 ,  H05K2203/0315 ,  H05K2203/1142 ,  Y10T29/49126 ,  Y10T29/49128

公开(公告)号：EP1871152B1

公开(公告)日：2009-02-25

申请号：EP07109738.0

申请日：2007-06-06

Applicant: NITTO DENKO CORPORATION

Inventor： Ishii, Jun ,  Ooyabu, Yasunari ,  Thaveeprungsriporn, Visit

IPC: H05K1/02 ,  H05K1/05

CPC classification number: H05K1/0259 ,  G11B5/484 ,  G11B5/486 ,  H05K1/056 ,  H05K1/167 ,  H05K2201/09554 ,  Y10T428/1328 ,  Y10T428/1393 ,  Y10T428/256 ,  Y10T428/257

Abstract: A wired circuit board has a metal supporting board (2), an insulating layer (3) formed on the metal supporting board, a conductive pattern (4) formed on the insulating layer and having a pair of wires (9a,9b) arranged in spaced-apart relation, and a semiconductive layer (5) formed on the insulating layer (3) and electrically connected to the metal supporting board (2) and the conductive pattern (4). The conductive pattern has a first region (14) in which a distance (D1) between the pair of wires is small and a second region (15) in which the distance (D2) between the pair of wires is larger than that in the first region. The semiconductive layer (5) is provided in the second region (15).

公开(公告)号：EP1865759A2

公开(公告)日：2007-12-12

申请号：EP07106018.0

申请日：2007-04-12

Applicant: NITTO DENKO CORPORATION

Inventor： Ooyabu, Yasunari, c/o Nitto Denko Corporation ,  Ishii, Jun, c/o Nitto Denko Corporation

IPC: H05K1/02

CPC classification number: H05K1/0259 ,  G11B5/484 ,  G11B5/486 ,  H05K1/056 ,  H05K1/167 ,  H05K3/28 ,  H05K2201/09554

Abstract: A wired circuit board has a metal supporting board, an insulating base layer formed on the metal supporting board, a conductive pattern formed on the insulating base layer and including at least one pair of wires arranged in mutually spaced-apart and opposed relation having different potentials, a semiconductive layer formed on the insulating base layer to cover the conductive pattern and electrically connected to the metal supporting board on one side outside a region where the pair of wires are opposed, and an insulating cover layer formed on the semiconductive layer.

Abstract translation: 布线电路基板具有：金属支承基板;形成在该金属支承基板上的基底绝缘层;形成在该基底绝缘层上的导电图案，该导电图案包括至少一对以相互分离且相对的关系配置的导线，该导线具有不同的电位 形成在基底绝缘层上以覆盖导电图案并在一对导线相对的区域外侧的一侧电连接到金属支撑板的半导体层以及形成在半导体层上的绝缘覆盖层。

公开(公告)号：EP0987748A3

公开(公告)日：2005-05-11

申请号：EP99118391.4

申请日：1999-09-16

Applicant: NEC Compound Semiconductor Devices, Ltd. ,  Fuchigami Micro Co.,Ltd.

Inventor： Hirasawa, Koki. ,  Ono, Teruo

IPC: H01L21/48 ,  H01L23/538

CPC classification number: H05K3/4629 ,  H01L21/4857 ,  H01L23/49805 ,  H01L23/5383 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01039 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/12042 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0306 ,  H05K1/056 ,  H05K3/423 ,  H05K3/44 ,  H05K3/4617 ,  H05K3/4652 ,  H05K2201/09554 ,  H05K2201/09563 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: A multilayered circuit board for a semiconductor chip module includes an underlying board, insulating layers, fixed-potential wiring layers, via holes, and metal layers. The underlying board has a major surface made of a metal material to which a fixed potential is applied. The insulating layers are stacked on the major surface of the underlying board and have wiring layers formed on their surfaces. The fixed-potential wiring layers constitute part of the wiring layers formed on the insulating layers. The via holes are formed below the fixed-potential wiring layers to extend through the insulating layers. The metal layers are filled in the via holes so as to make upper ends be connected to the lower surfaces of the fixed-potential wiring layers. One of the insulating layers in contact with the major surface of the underlying board is formed on the underlying board while the lower end of the metal layer is in contact with the major surface of the underlying board. The other insulating layer formed on the insulating layer in contact with the major surface of the underlying board is stacked while the lower end of the metal layer is in contact with the upper surface of the fixed-potential wiring layer of one insulating layer.

公开(公告)号：EP1523867A1

公开(公告)日：2005-04-20

申请号：EP03762156.2

申请日：2003-06-27

Applicant: PPG Industries Ohio, Inc.

Inventor： MCCOLLUM, Gregory J. ,  MORIARITY, Thomas C. ,  OLSON, Kevin C. ,  SANDALA, Michael G. ,  WANG, Alan E. ,  ZAWACKY, Steven R.

IPC: H05K1/05 ,  H05K3/44 ,  H01L23/498 ,  C09D5/44

CPC classification number: H05K3/44 ,  H01L2924/0002 ,  H05K1/056 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/445 ,  H05K2201/09554 ,  H05K2203/0582 ,  H05K2203/135 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Provided is a process for forming metallized vias in a substrate including the steps of (I) applying to an electroconductive substrate an electrodepositable coating composition onto all exposed surfaces of the substrate to form a conformal dielectric coating; (II) ablating a surface of the dielectric coating to expose a section of the substrate; (III) applying a layer of metal to all surfaces to form metallized vias in the substrate. Also disclosed are processes for fabricating a circuit assembly which include the application of an electrodoepositable coating composition onto exposed surfaces of the substrate/core to form a conformal dielectric coating thereon. The electrodepositable coating composition includes a resinous phase dispersed in an aqueous phase, where the resinous phase has a covalently bonded halogen content of at least 1 percent by weight. The dielectric coating derived therefrom has a low dielectric constant and low dielectric loss factor.

公开(公告)号：EP1520454A1

公开(公告)日：2005-04-06

申请号：EP03762158.8

申请日：2003-06-27

Applicant: PPG Industries Ohio, Inc.

Inventor： WANG, Alan E. ,  OLSON, Kevin C. ,  DI STEFANO, Thomas H.

IPC: H05K3/44 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09554 ,  H05K2201/10446 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A circuit board layer (2) in accordance with the present invention includes a conductive sheet (4) sandwiched between an insulating top layer (10) and an insulating bottom layer (14). The top and bottom layers (10) and (14) and the conductive sheet (4) define the circuit board layer (2) having an edge that includes an edge (20) of the conductive sheet (4). An insulating edge layer (18) covers substantially all of the edge (20) of the conductive sheet (4).

Abstract translation: 提供了一种形成一个电路板，包括（a）提供第一导电片的方法; （B）选择性地去除所述第一导电片材的一个或多个部分，以形成具有第一电路板没有被连接到通过至少一个标签中的第一面板的一个一次性部分的确从在所述第一电路板的边缘延伸的第一面板 于在所述第一面板的一次性部分的边缘; （C）施加到绝缘涂层至第一电路板，从而确实至少所述第一电路板的每个边缘从而覆盖; 和（d）在第一电路板从一次性部分的方式在所述片的至少一部分，其中分离保持附接至所述第一电路板和包括在所述第一电路板的所述导电片的暴露边缘。 因此，提供通过该方法形成的电路板。

公开(公告)号：EP1376778A2

公开(公告)日：2004-01-02

申请号：EP03013007.4

申请日：2003-06-10

Applicant: MOTOROLA, INC.

Inventor： Poglitsch, Lawrence R. ,  Li, Ronald ,  Kang, Alan S. ,  Ringa, Todd ,  Sharkey, Steven G. ,  Cihak, Rick

IPC: H01R13/658

CPC classification number: H05K3/363 ,  H01R13/58 ,  H01R43/0256 ,  H05K1/0215 ,  H05K1/0271 ,  H05K3/0061 ,  H05K3/4038 ,  H05K3/44 ,  H05K2201/0305 ,  H05K2201/09063 ,  H05K2201/09554

Abstract: A ground connector assembly (20) having a substrate (22) and a ground member (24). The substrate (22) is used to retain an electrical circuit and has a ground region (34), a ground hole (30), and at least one strain relief slot (32). The ground member (24) is attached within the ground hole (30). The ground region (34) surrounds the ground hole (30) and is at least partially interposed between the ground hole (30) and the strain relief slot (32). The ground connector assembly (20) may further include a conductive ring (42), such as a copper ring, surrounding the ground hole (30) and attached to the ground region (34). There is also a method of making the ground connector assembly (20).

Abstract translation: 一种具有基板（22）和接地构件（24）的接地连接器组件（20）。 基板（22）用于保持电路并具有接地区域（34），接地孔（30）和至少一个应变消除槽（32）。 接地构件（24）连接在接地孔（30）内。 接地区域（34）围绕接地孔（30）并且至少部分地插入接地孔（30）和应变消除槽（32）之间。 接地连接器组件（20）还可以包括围绕接地孔（30）并附接到接地区（34）的导电环（42），例如铜环。 还有一种制造接地连接器组件（20）的方法。