公开(公告)号：HK1073965A1

公开(公告)日：2005-10-21

申请号：HK05106338

申请日：2005-07-25

Applicant: TESSERA INTERCONNECT MATERIALS INC

Inventor： IIJIMA TOMOO ,  ENDO KIMITAKA ,  IKENAGA KAZUO ,  ODAIRA HIROSHI ,  MINARI NAOTO ,  KATO TAKASHI

IPC: H05K1/02 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K20100101 ,  H05K1/00 ,  H05K1/11 ,  H05K1/16 ,  H05K3/06 ,  H05K3/10 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  H05K3/46

Abstract: A manufacturing method for a wiring circuit board includes the steps of: forming a board on a surface of a metal layer directly or indirectly through an etching barrier layer; forming an insulating film on the surface of the metal layer; polishing the insulating film to an extent to which a top face of the bump is exposed; and forming a solder ball on the top face of the bump.

公开(公告)号：WO2010021685A1

公开(公告)日：2010-02-25

申请号：PCT/US2009/004694

申请日：2009-08-14

Applicant: TESSERA INTERCONNECT MATERIALS, INC. ,  HABA, Belgacem ,  RYU, Chang, Myung ,  ENDO, Kimitaka ,  WADE, Christopher, Paul

Inventor： HABA, Belgacem ,  RYU, Chang, Myung ,  ENDO, Kimitaka ,  WADE, Christopher, Paul

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L24/89 ,  H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13017 ,  H01L2224/13021 ,  H01L2224/13609 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An interconnection element 110 can include a substrate, e.g., a connection substrate, element of a package, circuit panel or microelectronic substrate, e.g., semiconductor chip, the substrate having a plurality of metal conductive elements such as conductive pads 112, contacts, bond pads, traces, or the like exposed at the surface. A plurality of solid metal posts 130 may overlie and project away from respective ones of the conductive elements. An intermetallic layer 121 can be disposed between the posts and the conductive elements, such layer providing electrically conductive interconnection between the posts 130 and the conductive elements 112. Bases of the posts adjacent to the intermetallic layer can be aligned with the intermetallic layer.

Abstract translation: 互连元件110可以包括衬底，例如连接衬底，封装的元件，电路板或微电子衬底，例如半导体芯片，衬底具有多个金属导电元件，例如导电焊盘112，触点，接合焊盘 ，痕迹等暴露在表面。 多个固体金属柱130可以覆盖并突出远离相应的导电元件。 金属间层121可以设置在柱和导电元件之间，这样的层提供柱130和导电元件112之间的导电互连。邻接金属间层的柱的基座可以与金属间层对准。

公开(公告)号：WO2008076428A1

公开(公告)日：2008-06-26

申请号：PCT/US2007/025841

申请日：2007-12-17

Applicant: TESSERA INTERCONNECT MATERIALS, INC. ,  ENDO, Kimitaka

Inventor： ENDO, Kimitaka

IPC: H01L23/538 ,  H01L23/50 ,  H01L21/48

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/50 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H05K1/0231 ,  H05K1/188 ,  H05K3/243 ,  H05K3/328 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/10636 ,  H05K2203/0369 ,  H05K2203/0384 ,  Y02P70/611 ,  Y10T29/49144 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A multiple wiring layer interconnection element (100) includes capacitors (110) or other electrical components embedded between a first exposed wiring layer (120) and a second exposed wiring layer (122) of the interconnection element (100). Internal wiring layers (124) and (126) are provided between exposed surfaces (112) of the respective capacitors (110), the internal wiring layers being electrically insulated from the capacitors (110) by dielectric layers (114) and (116), respectively. The internal wiring layers (124), (126) are isolated from each other by an internal dielectric layer (130). Conductive vias (132) provide conductive interconnection between the two internal wiring layers (124, 126). A method of fabricating a multiple wiring layer interconnection element is also provided.

Abstract translation: 多个布线层互连元件（100）包括电容器（110）或嵌入在互连元件（100）的第一暴露布线层（120）和第二暴露布线层（122）之间的其它电气部件。 内部布线层（124）和（126）设置在相应电容器（110）的暴露表面（112）之间，内部布线层通过电介质层（114）和（116）与电容器（110）电绝缘， 分别。 内部布线层（124），（126）通过内部电介质层（130）彼此隔离。 导电通孔（132）在两个内部布线层（124,126）之间提供导电互连。 还提供了制造多重布线层互连元件的方法。

公开(公告)号：EP1821588A1

公开(公告)日：2007-08-22

申请号：EP05788279.7

申请日：2005-09-29

Applicant: Sony Chemical & Information Device Corporation ,  Tessera Interconnect Materials, Inc.

Inventor： SHIMIZU, Kazuhiro c/o Sony Chemical & Information Device Corporation ,  YAGI, Masanobu c/o Sony Chemical & Information Device Corporation ,  HANAMURA, Kenichiro c/o Sony Chemical & Information Device Corporation ,  TAKAYASU, Mitsuyuki c/o Sony Chemical & Information Device Corporation ,  NAGAI, Kiyoe c/o Sony Chemical & Information Device Corporation ,  IIJIMA, Tomoo North Corporation,

IPC: H05K3/46

CPC classification number: H05K3/4038 ,  B32B37/26 ,  B32B2457/08 ,  H05K3/022 ,  H05K3/06 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1461 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49163

Abstract: A process for manufacturing a multilayer wiring board including the steps of forming an insulating layer on a base provided with a bump for interlayer connection, bonding a copper foil onto the insulating layer by a thermocompression bonding by sandwiching the copper foil between stainless steel plates, and patterning the copper foil, in which a metal foil is interposed at least between each of the stainless plates and the copper foil at the time of the thermocompression bonding. At this time, a mold release layer is formed on a surface of the metal foil to be imposed. Thus, such a multilayer wiring board can be manufactured that prevents sticking of a product after molding (cementing of the copper foil) and excels in dimensional stability without occurrence of wrinkling and ruggedness.

Abstract translation: 一种多层布线板的制造方法，其特征在于，在具有层间连接用凸块的基体上形成绝缘层的工序，将铜箔夹在不锈钢板之间，通过热压接将铜箔接合在绝缘层上， 在热压接时，至少在每个不锈钢板和铜箔之间插入金属箔的铜箔图形化。 此时，在要施加的金属箔的表面上形成脱模层。 因此，可以制造这样的多层布线板，其防止成型后的产品粘附（铜箔的粘合），并且尺寸稳定性优异，而不会发生起皱和粗糙。

公开(公告)号：EP1377145A4

公开(公告)日：2008-07-30

申请号：EP02707177

申请日：2002-03-27

Applicant: TESSERA INTERCONNECT MATERIALS

Inventor： IIJIMA TOMOO ,  KATO YOSHIRO ,  ODAIRA HIROSHI ,  OHSAWA MASAYUKI ,  KUROSAWA INETARO ,  SAKUMA KAZUO ,  ASANO TOSHIHIKO ,  ENDO KIMITAKA

IPC: B24B1/00 ,  B24B7/22 ,  B24B37/04 ,  H05K3/06 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11

CPC classification number: H05K3/4647 ,  B24B1/00 ,  B24B7/228 ,  B24B37/04 ,  H05K3/025 ,  H05K3/06 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2203/0143 ,  H05K2203/025 ,  H05K2203/0315 ,  H05K2203/0384 ,  H05K2203/0542 ,  H05K2203/061 ,  H05K2203/063 ,  H05K2203/1157

Abstract: A plurality of multilayer metal sheets (1) each comprising a bump-forming metal layer (2), etching-stop layer (3), and a wiring film-forming metal layer (4) are processed so as to each have a wiring film (4a) formed out of the wiring film-forming metal layer and bumps (2a) formed out of the bump-forming metal layer. The multilayer metal sheets are so stacked by repeating a stacking step in such a way that the bump-forming surface of one multilayer metal sheet faces to the wiring film of another multilayer metal sheet. A multilayer wiring board is polished by a polisher (11a) for a multilayer wiring board comprising a metal sheet holding means (13) for holding a metal sheet (1a), a blade holding means (25) for holding a blade (26) above the metal sheet, a height adjusting mechanism (20) for adjusting the height of the blade holding means, and a blade translating mechanism (15) for moving the blade holding means parallel to the surface of the metal sheet.

公开(公告)号：US20130119012A1

公开(公告)日：2013-05-16

申请号：US13661888

申请日：2012-10-26

Applicant: TESSERA INTERCONNECT MATERIALS, INC.

Inventor： Kimitaka Endo

IPC: H01R43/02

CPC classification number: H01R43/0256 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13609 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01322 ,  H05K1/185 ,  H05K3/06 ,  H05K3/4007 ,  H05K3/4015 ,  H05K3/4614 ,  H05K2201/0355 ,  H05K2201/0361 ,  H05K2201/10674 ,  H05K2203/0384 ,  H05K2203/0542 ,  H01L2224/05599

Abstract: An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.

Abstract translation: 公开了互连元件及其制造方法。 互连元件可以包括多个金属导体，多个固体金属凸块和低熔点（LMP）金属层。 固体金属凸起并且远离相应导体的第一方向突出。 每个凸块具有至少一个沿至少一个横向于第一方向的第二方向限定凸块的边缘。 低熔点（LMP）金属层具有通过至少一个边缘和与凸块接合的第二面连接到各个导体并沿第二方向限定的第一面。 凸块和LMP层的边缘在第一方向上对齐，并且LMP金属层的熔化温度基本上低于导体。

公开(公告)号：EP2288244A1

公开(公告)日：2011-02-23

申请号：EP10011151.7

申请日：2000-10-11

Applicant: Tessera Interconnect Materials, Inc.

Inventor： Tomo, Ijima ,  Masayuji, Ohsawa

IPC: H05K3/40 ,  H05K3/46 ,  H05K3/06

CPC classification number: H05K3/4647 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/06 ,  H05K3/062 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/0384 ,  H05K2203/041 ,  H05K2203/0733 ,  H05K2203/1189 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49137 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: The invention relates to a wiring circuit substrate, comprising: a first metal layer in which conductor circuit traces (32) are formed; etched metal protrusions that are in direct contact with said first metal layer; and a second metal layer that is formed on side surfaces of said protrusions, wherein said second metal layer is formed of a solder-plated layer.

Abstract translation: 布线电路基板技术领域本发明涉及一种布线电路基板，其包括：形成有导体电路布线（32）的第一金属层; 蚀刻的金属突起，其与所述第一金属层直接接触; 以及形成在所述突起的侧表面上的第二金属层，其中所述第二金属层由焊料镀层形成。

公开(公告)号：EP1821588A4

公开(公告)日：2009-11-11

申请号：EP05788279

申请日：2005-09-29

Applicant: SONY CHEM & INF DEVICE CORP ,  TESSERA INTERCONNECT MATERIALS

Inventor： SHIMIZU KAZUHIRO ,  YAGI MASANOBU ,  HANAMURA KENICHIRO ,  TAKAYASU MITSUYUKI ,  NAGAI KIYOE ,  IIJIMA TOMOO

IPC: H05K3/46 ,  B32B37/26

CPC classification number: H05K3/4038 ,  B32B37/26 ,  B32B2457/08 ,  H05K3/022 ,  H05K3/06 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1461 ,  Y10T29/49128 ,  Y10T29/49156 ,  Y10T29/49163

公开(公告)号：EP2880685A1

公开(公告)日：2015-06-10

申请号：EP13750213.4

申请日：2013-08-01

Applicant: Tessera Interconnect Materials, Inc.

Inventor： HABA, Belgacem ,  ZOHNI, Wael ,  CRISP, Richard Dewitt ,  MOHAMMED, Ilyas ,  LAMBRECHT, Frank

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00

CPC classification number: H01L23/13 ,  H01L23/49816 ,  H01L23/50 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/05555 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/49095 ,  H01L2224/49175 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A microelectronic assembly (100) can include a substrate (102) having first and second surfaces (104, 106) each extending in first and second transverse directions D1, D2, a peripheral edge (3) extending in the second direction, first and second openings (116, 126) extending between the first and second surfaces, and a peripheral region P1 of the second surface extending between the peripheral edge and one of the openings. The assembly (100) can also include a first microelectronic element (136) having an edge (146) extending between front and rear surfaces (140, 138) thereof and a second microelectronic element (153) having a front surface (157) facing the rear surface of the first microelectronic element and projecting beyond the edge. The assembly (100) can also include a plurality of terminals (110) exposed at the second surface (106), at least one of the terminals (110a) being disposed at least partially within the peripheral region P1.

公开(公告)号：EP2306797A1

公开(公告)日：2011-04-06

申请号：EP10011153.3

申请日：2000-10-11

Applicant: Tessera Interconnect Materials, Inc.

Inventor： Ijima, Tomo ,  Ohsawa, Masayuji

IPC: H05K3/40 ,  H05K3/46 ,  H05K3/06 ,  H05K3/34

CPC classification number: H05K3/4647 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/81192 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/06 ,  H05K3/062 ,  H05K3/3457 ,  H05K3/4038 ,  H05K3/4614 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/0384 ,  H05K2203/041 ,  H05K2203/0733 ,  H05K2203/1189 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49137 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: The invention relates to a wiring circuit substrate, comprising: an insulating layer (306) having a face on which a first metal layer (307) is patterned; etched protrusions (308) projecting from said first metal layer in a state of passing through said insulating layer and formed of a conductor-forming metal; and a plurality of solder balls (315) or solder bumps (314) formed selectively on a surface of the first metal layer opposite from the etched protrusions, at least some of the solder balls or solder bumps being at least partly aligned with the etched protrusions.

Abstract translation: 本发明涉及一种布线电路基板，包括：绝缘层（306），其具有其上图案化第一金属层（307）的面; 在穿过所述绝缘层并由导体形成金属形成的状态下从所述第一金属层突出的蚀刻突起（308） 和多个焊球（315）或焊料凸块（314），所述焊球（315）或焊料凸块（314）选择性地形成在所述第一金属层的与所述蚀刻突起相对的表面上，所述焊球或焊料凸块中的至少一些至少部分地与所述蚀刻突起 。