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公开(公告)号：KR1020160045440A
公开(公告)日：2016-04-27
申请号：KR1020140140977
申请日：2014-10-17
Applicant: 삼성전자주식회사
IPC: H01L29/78 , H01L21/336
CPC classification number: H01L29/66795 , H01L21/76229 , H01L29/66545 , H01L29/785 , H01L29/7843 , H01L29/7855
Abstract: 제1 컷필드게이트패턴및 제1 핀게이트패턴을포함하고, 상기제1 컷필드게이트패턴은제1 부분에서절연성제1 컷필드게이트코어, 및제2 부분에서전도성제1 컷필드게이트전극을포함하고, 상기제1 핀게이트패턴은제1 부분에서절연성제1 핀게이트코어를포함하고, 및제2 부분에서전도성제1 핀게이트전극을포함하고, 상기제1 컷필드게이트코어의상면및 상기제1 핀게이트코어의상면은공면(co-planar)을갖는반도체소자가설명된다.
Abstract translation: 公开了一种包括第一切割场栅极图案和第一鳍状栅极图案的半导体器件。 第一切割场栅极图案包括：第一区域中的绝缘第一场栅极核心; 以及在第二区域中的导电的第一切割场栅极电极。 第一鳍栅极图案包括：第一区域中的绝缘第一场栅核心; 和第二区域中的导电第一切割场栅极电极。 第一切割磁场门芯的上表面和散热片门芯的上表面被构造成具有共面表面。 本发明的目的是提供一种具有栅芯和鳍片活性芯的半导体。
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公开(公告)号：KR1020070084833A
公开(公告)日：2007-08-27
申请号：KR1020060017100
申请日：2006-02-22
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/823475 , H01L21/76897 , H01L21/823468
Abstract: A method for forming a contact of a semiconductor device is provided to prevent throughput decrease and generation of short phenomenon between adjacent contacts by forming a contact hole having a second spacer on a preliminary contact hole. A conductive layer pattern(106) and a mask pattern(108) are laminated on a semiconductor substrate(100). A conductive structure including a first spacer(112) is formed sidewalls of the conductive layer pattern and the mask pattern. Silicon germanium covering the conductive structure is deposited on the semiconductor substrate to form a sacrificial layer. The sacrificial layer is partially etched to form a preliminary contact hole exposing the semiconductor substrate between the conductive structures. Thin films for a spacer are successively formed on the surfaces of the preliminary contact hole and the sacrificial layer. The thin film for spacer on the external sidewall of the preliminary contact hole is anisotropic-etched to form a contact hole(120) having a second spacer. A conductive material is gap-filled in the contact hole to form a contact. The sacrificial layer is then removed. An interlayer dielectric is formed on a part where the sacrificial layer is removed.
Abstract translation: 提供一种用于形成半导体器件的接触的方法，以通过在预接触孔上形成具有第二间隔物的接触孔来防止相邻触点之间的通过量减少和短暂现象的产生。 导电层图案（106）和掩模图案（108）层压在半导体衬底（100）上。 包括第一间隔物（112）的导电结构形成在导电层图案和掩模图案的侧壁上。 覆盖导电结构的硅锗沉积在半导体衬底上以形成牺牲层。 牺牲层被部分蚀刻以形成在导电结构之间暴露半导体衬底的预接触孔。 用于间隔物的薄膜依次形成在预接触孔和牺牲层的表面上。 在预接触孔的外侧壁上的用于间隔物的薄膜被各向异性蚀刻以形成具有第二间隔物的接触孔（120）。 导电材料在接触孔中间隙填充以形成接触。 然后去除牺牲层。 在去除牺牲层的部分上形成层间电介质。
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公开(公告)号：KR1020070040633A
公开(公告)日：2007-04-17
申请号：KR1020050096164
申请日：2005-10-12
Applicant: 삼성전자주식회사
Inventor： 배근희
IPC: H01L21/3065
CPC classification number: H01L21/31116 , H01L21/02063 , H01L21/0214 , H01L21/02362 , H01L21/3146
Abstract: A method of etching a carbon-containing layer on a semiconductor substrate using a Si-containing gas and a related method of fabricating a semiconductor device in which a plurality of contact holes having excellent sidewall profiles are formed by etching an interlayer insulating layer using a carbon-containing layer pattern formed in accordance with the invention and having a width of several tens of nm as an etch mask are provided. To etch a carbon-containing layer to be used as a second etch mask, a first mask pattern is formed on the carbon-containing layer to partially expose a top surface of the carbon-containing layer. The carbon-containing layer is then anisotropically etched with a plasma of a carbon-etching mixture gas formed of O2 and a Si-containing gas using the first mask pattern as a first etch mask to form the carbon-containing layer pattern. Neighboring contact holes in a high-density cell array region fabricated in accordance with this invention are distinctly separated from each other, even when an interval between the neighboring contact holes is as small as several tens of nm or less; and, thus, a short-circuit between neighboring unit cells using such contact holes can be prevented.
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公开(公告)号：KR1020070027910A
公开(公告)日：2007-03-12
申请号：KR1020050079835
申请日：2005-08-30
Applicant: 삼성전자주식회사
IPC: H01L21/28
CPC classification number: H01L21/76889 , H01L21/02068 , H01L21/2652 , H01L21/76814
Abstract: A contact forming method and a method for forming a semiconductor device using the same are provided to reduce resistance of a contact by removing selectively a metallic film from an unwanted portion using a predetermined cleaning solution containing a phosphoric acid, an acetic acid and a nitric acid. An insulating layer(102) is formed on a silicon substrate(100). A contact hole for exposing partially the substrate to the outside is formed through the insulating layer. A metallic film is formed along an upper surface of the resultant structure. A metal silicide pattern(110) is formed on a bottom of the contact hole by reacting the metallic film on the substrate. The metallic film is selectively removed from an unwanted portion of the resultant structure by using a predetermined cleaning solution containing a phosphoric acid, an acetic acid and a nitric acid. A conductive layer(112) for filling the contact hole is formed on the resultant structure.
Abstract translation: 提供接触形成方法和使用其形成半导体器件的方法，以通过使用含有磷酸，乙酸和硝酸的预定清洗溶液，从不期望的部分选择性地除去金属膜来降低接触电阻 。 在硅衬底（100）上形成绝缘层（102）。 通过绝缘层形成用于将衬底部分地暴露于外部的接触孔。 沿所得结构的上表面形成金属膜。 通过使基板上的金属膜反应，在接触孔的底部形成金属硅化物图案（110）。 通过使用含有磷酸，乙酸和硝酸的预定清洗溶液，从所得结构的不期望部分选择性地除去金属膜。 在所得结构上形成用于填充接触孔的导电层（112）。
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公开(公告)号：KR1020040079066A
公开(公告)日：2004-09-14
申请号：KR1020030013979
申请日：2003-03-06
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method for forming a contact hole of a semiconductor device is provided to facilitate formation of a contact hole by eliminating a gate electrode spacer before the contact hole is formed and by forming the contact hole after an interval between gate electrode structures is guaranteed. CONSTITUTION: Gate electrode structures are formed on a semiconductor substrate(100), separated from each other by a predetermined interval. The first spacer is formed on both sidewalls of the gate electrode structure. A junction region(135a,135b) is formed on the semiconductor substrate at both sides of the gate electrode structures. The first spacer is eliminated. An interlayer dielectric(145) is deposited on the resultant structure. The interlayer dielectric is etched to expose the junction region so that a contact hole(155) is formed. The second spacer(150) is formed on the sidewall of the contact hole.
Abstract translation: 目的：提供一种用于形成半导体器件的接触孔的方法，以便通过在形成接触孔之前消除栅极电极间隔件并且在保证栅电极结构之间的间隔之后形成接触孔来形成接触孔。 构成：栅极电极结构形成在半导体衬底（100）上，以预定的间隔彼此分开。 第一间隔物形成在栅电极结构的两个侧壁上。 在栅电极结构的两侧在半导体衬底上形成结区域（135a，135b）。 第一个间隔物被消除。 在所得结构上沉积层间电介质（145）。 蚀刻层间电介质以露出接合区域，从而形成接触孔（155）。 第二间隔件（150）形成在接触孔的侧壁上。
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Patent Agency Ranking
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公开(公告)号：KR1020160102788A
公开(公告)日：2016-08-31
申请号：KR1020150025303
申请日：2015-02-23
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L29/785 , H01L27/0886 , H01L27/0924 , H01L27/1211 , H01L29/0657 , H01L29/4238 , H01L29/495 , H01L29/7848 , H01L29/7831 , H01L29/7843 , H01L29/7855
Abstract: 반도체장치및 그제조방법이제공된다. 반도체장치는, 제1 방향으로연장된제1 액티브핀, 제1 액티브핀으로부터제1 방향과교차하는제2 방향으로이격되고, 제1 방향으로연장되고, 제1 액티브핀에비해짧은장변길이를갖는제2 액티브핀, 제1 및제2 액티브핀의일단과오버랩되어제2 방향으로연장된제1 더미게이트, 제1 액티브핀과교차하고제2 액티브핀의타단과오버랩되어제2 방향으로연장된제1 메탈게이트, 및제1 액티브핀과교차하고제2 방향으로연장된제1 절연게이트를포함하되, 제1 절연게이트는제1 액티브핀 내로연장된다.
Abstract translation: 提供了具有提高的产品可靠性的半导体器件及其制造方法。 半导体器件包括：沿第一方向延伸的第一有源销; 在与所述第一方向相交的第二方向上与所述第一有源销分离的第二有源引脚沿所述第一方向延伸，并且具有比所述第一有效引脚短的长边; 第一虚拟栅极与所述第一有源销的一端重叠，并且所述第二有源引脚在所述第二方向上延伸; 与所述第一有源销相交的第一金属栅极，与所述第二有源销的另一端重叠以在所述第二方向上延伸; 以及与所述第一有源销相交且在所述第二方向上延伸的第一绝缘栅极，其中所述第一绝缘栅极延伸到所述第一有源销的内部。
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公开(公告)号：KR1020160074859A
公开(公告)日：2016-06-29
申请号：KR1020140183490
申请日：2014-12-18
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L29/7848 , H01L29/165 , H01L29/66545 , H01L29/66818 , H01L29/7851 , H01L29/785
Abstract: 본발명의실시예에따른반도체장치는, 복수의활성영역들이정의된기판, 복수의활성영역들중 일부와교차되며제1 방향으로연장되고, 제1 방향에서서로인접하게배치되는제1 및제2 게이트전극들을포함하는복수의게이트전극들, 제1 및제2 게이트전극들의사이에배치되는게이트분리부를포함하고, 게이트분리부는, 제1 층및 제1 방향에수직한제2 방향에서제1 층의양단에배치되는제2 층을포함한다.
Abstract translation: 提供了具有改进的集成度的半导体器件，用于形成半导体器件的图案的方法和制造半导体器件的方法。 根据本发明的实施例，半导体器件包括：具有限定在其中的多个有源区的衬底; 多个栅极通过与有源区的一部分交叉而沿第一方向延伸，并且包括沿第一方向彼此相邻布置的第一和第二栅极; 以及布置在所述第一和第二栅电极之间的栅极分离单元。 门分离单元包括：第一层; 以及在垂直于第一方向的第二方向上布置在第一层的两端上的第二层。
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公开(公告)号：KR101489326B1
公开(公告)日：2015-02-11
申请号：KR1020080088915
申请日：2008-09-09
Applicant: 삼성전자주식회사
IPC: H01L21/205
CPC classification number: C23C16/505 , C23C16/45523 , C23C16/52 , H01J37/321 , H01J37/32146 , H01J37/32449 , H01L21/02164 , H01L21/0217 , H01L21/02274 , H01L21/0228 , H01L21/31608 , H01L21/3185
Abstract: 플라즈마를 이용한 기판의 처리 방법이 제공된다. 이에 따르면, 챔버 내에 기판을 로딩한다. 상기 챔버 내에서 제 1 플라즈마 모드로 상기 기판을 1차 처리한다. 상기 챔버 내에서 제 2 플라즈마 모드로 상기 기판을 2차 처리한다. 상기 제 1 플라즈마 모드 및 상기 제 2 플라즈마 모드 가운데 적어도 하나는 상기 기판에 발생하는 플라즈마 대전 손상을 줄이기 위해서 상기 챔버 내에 유도되는 플라즈마의 온 및 오프를 반복하는 시간 변조 모드이고, 상기 시간 변조 모드는 상기 챔버 내에 플라즈마를 유도하기 위해 상기 기판 위의 상부 전극에 공급된 상부 RF 파워 및 상기 기판 아래의 하부 전극에 공급된 바닥 RF 파워를 동시에 주기적으로 온(on) 및 오프(off)시켜 수행한다.
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公开(公告)号：KR1020100012970A
公开(公告)日：2010-02-09
申请号：KR1020080074429
申请日：2008-07-30
Applicant: 삼성전자주식회사
IPC: H01L21/306 , H01L21/687 , H01L21/66
CPC classification number: H01J37/32963 , H01L21/67069
Abstract: PURPOSE: Equipment for manufacturing semiconductor devices is provided to maximize measurement reliability by sensing the light in the infrared rays of a plasma reaction generated inside a chamber. CONSTITUTION: A chamber(20) provides a space separated from the outside. An electrostatic chuck(22) inside the chamber supports the wafer. A bottom electrode(24) is formed inside the electrostatic chuck or in the lower part and receives a high frequency power for exciting the reaction gas flowing in the wafer. A top electrode(26) is formed on the wafer facing with the bottom electrode. An endpoint detector(30) includes an optical fiber(32) connected to the upper part of the top electrode. A collimator is formed between the optical fiber and the top electrode.
Abstract translation: 目的：提供用于制造半导体器件的设备，以通过感测室内产生的等离子体反应的红外线中的光来最大化测量可靠性。 构成：室（20）提供与外部分离的空间。 室内的静电卡盘（22）支撑晶片。 底部电极（24）形成在静电卡盘内部或下部，并且接收用于激发在晶片中流动的反应气体的高频电力。 在与底部电极相对的晶片上形成顶部电极（26）。 端点检测器（30）包括连接到顶部电极的上部的光纤（32）。 在光纤和顶部电极之间形成准直器。
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