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公开(公告)号：KR1020030037571A
公开(公告)日：2003-05-14
申请号：KR1020010068820
申请日：2001-11-06
Applicant: 삼성전자주식회사
IPC: H01L21/762
CPC classification number: H01L21/76264 , H01L21/76283
Abstract: PURPOSE: A semiconductor device having trench isolation structure and a manufacturing method thereof are provided to prevent the stress induced defect of a silicon layer by forming a trench having a shallow and deep trench. CONSTITUTION: An SOI(Silicon On Insulator) substrate composed of a base substrate(200), a buried insulator layer(202) and an upper silicon layer(204), is provided with a trench region(214) located at the predetermined portion of the same and an isolation structure(228) for filling in the trench region(214). At this time, trench region(214) further includes a deep trench region(214d) formed through the upper silicon layer(204) to the upper surface of the buried insulator layer(202), and a shallow trench region(214s) formed at the peripheral portion of the deep trench region(214d). The isolation structure(228) further comprises a trench oxide layer(216), a trench liner(218a) and an isolating layer pattern(224p) for filling in the trench region(214).
Abstract translation: 目的：提供具有沟槽隔离结构的半导体器件及其制造方法，通过形成具有浅沟槽和深沟槽的沟槽来防止硅层的应力引起的缺陷。 构成：由基底基板（200），掩埋绝缘体层（202）和上硅层（204）组成的SOI（绝缘体上硅）基板设置有位于预定部分的沟槽区域（214） 相同的和用于填充沟槽区域（214）的隔离结构（228）。 此时，沟槽区域（214）还包括通过上硅层（204）到掩埋绝缘体层（202）的上表面形成的深沟槽区域（214d）和形成在 深沟槽区域（214d）的周边部分。 隔离结构（228）还包括用于填充沟槽区域（214）的沟槽氧化物层（216），沟槽衬垫（218a）和隔离层图案（224p）。
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公开(公告)号：KR1020090120119A
公开(公告)日：2009-11-24
申请号：KR1020080046000
申请日：2008-05-19
Applicant: 삼성전자주식회사
IPC: H01L29/78
CPC classification number: H01L29/4234 , H01L27/11568 , H01L27/11573 , H01L29/792
Abstract: PURPOSE: A fine transistor and a method for manufacturing the same are provided to make a manufacturing process simple by forming a space through a round etching and forming a SONOS cell using a charge trap layer. CONSTITUTION: In a fine transistor and a method for manufacturing the same, a tunnel oxide film is formed on a semiconductor substrate(100). A nitride film and a passivation are formed on the tunnel oxide film(110), and the passivation is pattern and is used as a mask to etch the nitride film, and charge trapping layers(123) which are separated from each other. A blocking insulation film(124) is formed on a formed nitride film, and an electrode is formed on the blocking oxide film and the tunnel oxide film.
Abstract translation: 目的：提供精细晶体管及其制造方法，以通过圆形蚀刻形成空间并使用电荷陷阱层形成SONOS电池来简化制造工艺。 构成：在微细晶体管及其制造方法中，在半导体衬底（100）上形成隧道氧化膜。 在隧道氧化膜（110）上形成氮化物膜和钝化层，并且钝化是图案，并用作掩模以蚀刻氮化物膜，并对彼此分离的电荷俘获层（123）进行充电。 在形成的氮化物膜上形成阻挡绝缘膜（124），并且在阻挡氧化膜和隧道氧化物膜上形成电极。
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13.发明授权측정의 신뢰도를 향상시킬 수 있는 측정용 패턴을구비하는 반도체장치 및 측정용 패턴을 이용한반도체장치의 측정방법 有权具有提高测量可靠性的测量图案的半导体器件和使用测量图案测量半导体器件的方法
公开(公告)号：KR100546330B1
公开(公告)日：2006-01-26
申请号：KR1020030035603
申请日：2003-06-03
Applicant: 삼성전자주식회사
IPC: H01L21/027
CPC classification number: H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: 측정용 패턴을 개선하여 측정의 신뢰도를 향상시킬 수 있는 측정용 패턴을 구비하는 반도체장치 및 이를 이용한 반도체장치의 측정방법이 개시된다. 본 발명에 따른 측정용 패턴을 구비하는 반도체장치는, 반도체 집적회로가 형성되는 칩영역과 상기 칩영역을 둘러싸는 스크라이브영역을 포함하는 반도체기판; 상기 스크라이브영역 내의 상기 반도체기판의 표면에 빈 공간의 형태로 형성되며, 계측설비의 측정용 빔이 투사되는 빔영역이 포함될 수 있도록 일정한 표면 단면적을 갖는 측정용 패턴; 및 상기 측정용 패턴의 내부에, 상기 측정용 패턴의 빈 공간의 표면 단면적을 감소, 예를 들어 빔영역의 표면 단면적 대비 더미 패턴의 표면 단면적의 비율이 5% 내지 15%가 될 수 있도록 더미 패턴을 포함한다.
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公开(公告)号：KR1020050030741A
公开(公告)日：2005-03-31
申请号：KR1020030066826
申请日：2003-09-26
Applicant: 삼성전자주식회사
IPC: H01L27/115
Abstract: A split-gate type non-volatile memory device is provided to increase the voltage induced to a floating gate and improve a program characteristic by additionally forming the planarized second insulation layer on the first insulation layer. A semiconductor substrate(200) is prepared. A gate insulation layer pattern(230) is formed on the semiconductor substrate. A floating gate pattern(240) which is thinner in its center portion than both its edge portions is formed on the gate insulation layer pattern. An interpoly dielectric(270) is formed on the floating gate pattern, including the first and second insulation layers(250,260). The first insulation layer is thinner in both its edge portions than its center portion, The second insulation layer which is thicker in its center portion than both its edge portions to make the upper surface flat is formed on the first insulation layer. One sidewall of the resultant structure and the upper surface of the semiconductor substrate adjacent to the one sidewall are covered with a tunnel insulation layer pattern(290). A control gate pattern(300) is formed on the tunnel insulation layer pattern.
Abstract translation: 分离栅型非易失性存储器件被提供以通过在第一绝缘层上另外形成平坦化的第二绝缘层来增加感应到浮动栅极的电压并改善程序特性。 制备半导体衬底（200）。 在半导体衬底上形成栅极绝缘层图案（230）。 在栅极绝缘层图案上形成有比其两个边缘部分在其中心部分更薄的浮栅图案（240）。 在浮栅图案上形成多层电介质（270），包括第一和第二绝缘层（250,260）。 第一绝缘层在其边缘部分比其中心部分更薄。在第一绝缘层上形成有在其中心部分比其两个边缘部分更厚以使上表面平坦的第二绝缘层。 所得结构的一个侧壁和与一个侧壁相邻的半导体衬底的上表面被隧道绝缘层图案（290）覆盖。 在隧道绝缘层图案上形成控制栅极图案（300）。
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公开(公告)号：KR1020040025286A
公开(公告)日：2004-03-24
申请号：KR1020020057191
申请日：2002-09-19
Applicant: 삼성전자주식회사
IPC: H01L27/115
CPC classification number: H01L27/11521 , H01L21/28273 , H01L27/115
Abstract: PURPOSE: A method for manufacturing a split gate type flash memory device is provided to be capable of forming a floating gate pattern without forming misalignment and approximity effect. CONSTITUTION: A trench isolation layer(58) is formed on a semiconductor substrate for defining a plurality of first active regions(62a) and a plurality of second active regions(62b). Floating gate patterns(64) spaced apart from each other are formed on the first active regions(62a) by etching a conductive pattern using an oxide pattern as a mask. A tunnel oxide layer is formed at both sidewalls of the floating gate patterns(64). A plurality of control gate electrodes are formed on the floating gate patterns.
Abstract translation: 目的：提供一种用于制造分离栅型闪存器件的方法，以能够形成浮栅图案而不形成不对准和近似效应。 构成：在半导体衬底上形成沟槽隔离层（58），用于限定多个第一有源区（62a）和多个第二有源区（62b）。 通过使用氧化物图案作为掩模蚀刻导电图案，在第一有源区域（62a）上形成彼此间隔开的浮动栅极图案（64）。 隧道氧化物层形成在浮置栅极图案（64）的两个侧壁处。 多个控制栅电极形成在浮栅图案上。
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Patent Agency Ranking
公开(公告)号：KR1020030063642A
公开(公告)日：2003-07-31
申请号：KR1020020003872
申请日：2002-01-23
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: PURPOSE: A method of manufacturing a semiconductor device having a borderless contact hole is provided to prevent a leakage current pass caused from the recess of a device isolation by over etch in the contact formation that exposes an impurity region and the nearest trench isolation layer at the same time. CONSTITUTION: A trench isolation layer formed on the first conductive type semiconductor substrate(101) is recessed to have a constant depth and the upper sidewall of an active region is exposed. By implanting the second impurity ion into the exposed upper sidewall, an impurity region(130) is formed on the surface of the active region and the exposed upper sidewall. An interlayer dielectric(109) is formed on the semiconductor substrate having the impurity region. By patterning the interlayer dielectric, a contact hole(110) that exposes simultaneously an impurity region and the nearest trench isolation layer is formed.
Abstract translation: 目的：提供一种制造具有无边界接触孔的半导体器件的方法，以防止在暴露杂质区域的接触形成中的过度蚀刻从设备隔离的凹部引起的漏电流通过，并且在最近的沟槽隔离层处 同时。 构成：形成在第一导电类型半导体衬底（101）上的沟槽隔离层凹入以具有恒定的深度，并且有源区的上侧壁被暴露。 通过将第二杂质离子注入到暴露的上侧壁中，在有源区和暴露的上侧壁的表面上形成杂质区（130）。 在具有杂质区域的半导体衬底上形成层间电介质（109）。 通过图案化层间电介质，形成同时暴露杂质区域和最近的沟槽隔离层的接触孔（110）。
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公开(公告)号：KR100812237B1
公开(公告)日：2008-03-10
申请号：KR1020060081082
申请日：2006-08-25
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L27/105 , H01L27/11526 , H01L27/11539 , H01L21/28273 , H01L21/31144
Abstract: A method for manufacturing an embedded flash memory device is provided to enhance the reliability of the embedded flash memory device by preventing deterioration of logic conformity in a logic region. A first region and a second region are defined on a semiconductor substrate(110). A floating gate structure is formed to interpose a first gate insulating layer pattern(114a) into the first region. A second gate insulating layer(125) is formed on the semiconductor substrate of the first region and the second region including the floating gate structure. A well is formed within the semiconductor substrate of the second region including the second gate insulating layer. The first and the second region correspond to a flash memory cell region and a logic region. The logic region includes a low voltage region and a high voltage region. The second gate insulating layer of the high voltage region is thicker than a first gate insulating layer pattern.
Abstract translation: 提供一种用于制造嵌入式闪速存储器件的方法，以通过防止逻辑区域中逻辑一致性的恶化来增强嵌入式闪存器件的可靠性。 第一区域和第二区域被限定在半导体衬底（110）上。 形成浮置栅极结构以将第一栅极绝缘层图案（114a）插入到第一区域中。 第二栅极绝缘层（125）形成在第一区域的半导体衬底上，而第二区域包括浮动栅极结构。 在包括第二栅极绝缘层的第二区域的半导体衬底内形成阱。 第一和第二区域对应于闪存单元区域和逻辑区域。 逻辑区域包括低电压区域和高电压区域。 高电压区域的第二栅极绝缘层比第一栅极绝缘层图案厚。
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公开(公告)号：KR1020070076934A
公开(公告)日：2007-07-25
申请号：KR1020060006449
申请日：2006-01-20
Applicant: 삼성전자주식회사
IPC: H01L27/115 , H01L21/8247
CPC classification number: H01L29/42324 , H01L27/115 , H01L27/11521 , H01L29/7885 , H01L27/11519
Abstract: A nonvolatile memory device and its manufacturing method are provided to reduce damage of the nonvolatile memory device due to ion implantation for forming a source region by minutely patterning a floating gate in a small size. A source region(260) is formed in a semiconductor substrate(100). A part of a gate dielectric is overlapped with the source region. A floating gate(220) is formed on an upper portion of the gate dielectric. Electric field of the floating gate is constantly formed on the region overlapped with the source region. A control gate(250) is formed to be insulated from an upper portion of the floating gate along a sidewall of the floating gate. An intergate dielectric is disposed between the floating gate and the control gate. A drain region(270) is formed in the proximity of the other side of the control gate. A side of the floating gate adjacent to the source region has a curvature smaller than the other side of the floating gate.
Abstract translation: 提供一种非易失性存储器件及其制造方法，用于通过用于通过以小尺寸精细构图浮栅来形成源极区域而减少由于离子注入引起的非易失性存储器件的损坏。 源区域（260）形成在半导体衬底（100）中。 栅极电介质的一部分与源极区域重叠。 在栅极电介质的上部形成浮栅（220）。 在与源极区域重叠的区域上，恒定地形成浮栅的电场。 控制栅极（250）形成为沿着浮动栅极的侧壁与浮动栅极的上部绝缘。 隔栅电介质设置在浮置栅极和控制栅极之间。 在控制栅极的另一侧附近形成漏区（270）。 与源极区域相邻的浮动栅极的一侧具有小于浮动栅极的另一侧的曲率。
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公开(公告)号：KR100718253B1
公开(公告)日：2007-05-16
申请号：KR1020050075126
申请日：2005-08-17
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L29/7881 , H01L21/28273 , H01L27/105 , H01L27/11526 , H01L27/11543 , H01L29/42324
Abstract: 개선된 팁 프로파일과 균일한 두께의 게이트 절연막을 갖는 스플릿 게이트 타입의 불휘발성 메모리 장치의 제조 방법에서, 제1 게이트 절연막 및 제1 도전막이 기판 상에 형성되며, 산화막 패턴은 상기 도전막을 부분적으로 산화시킴으로써 형성된다. 상기 산화막 패턴을 마스크로 사용하여 상기 제1 도전막을 식각함으로써 상기 제1 게이트 절연막 상에 플로팅 게이트 전극이 형성된다. 상기 플로팅 게이트 전극이 형성된 기판의 전체 표면 상에 제1 실리콘막을 형성한 후, 상기 제1 실리콘막을 산화시킴으로써 상기 플로팅 게이트 전극의 측면들 및 상기 플로팅 게이트 전극과 인접하는 상기 기판의 표면 부위들 상에 터널 절연막 및 제2 게이트 절연막이 각각 형성된다. 상기 터널 절연막 및 상기 제2 게이트 절연막 상에 컨트롤 게이트 전극을 형성한다. 상기 컨트롤 게이트 전극이 형성된 기판의 전체 표면 상에 제2 실리콘막을 형성하고, 상기 제2 실리콘막을 열산화막으로 형성한다.
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公开(公告)号：KR100699819B1
公开(公告)日：2007-03-27
申请号：KR1020010001895
申请日：2001-01-12
Applicant: 삼성전자주식회사
IPC: H01L21/334
Abstract: 반도체 기판 내부에 산화층이 형성된 모스 트랜지스터의 형성 방법에 관해 개시한다. 게이트 산화막을 형성하기 위한 산화층을 반도체 기판 내에 형성하고, 그 상면의 반도체 기판을 직접 식각하여 주입 깊이와 동일한 높이의 게이트를 형성함으로써, 두께가 얇고 안정성이 좋은 게이트 산화막을 형성할 수 있다.
산화층, 이온 주입
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