Abstract:
PURPOSE: A semiconductor device having trench isolation structure and a manufacturing method thereof are provided to prevent the stress induced defect of a silicon layer by forming a trench having a shallow and deep trench. CONSTITUTION: An SOI(Silicon On Insulator) substrate composed of a base substrate(200), a buried insulator layer(202) and an upper silicon layer(204), is provided with a trench region(214) located at the predetermined portion of the same and an isolation structure(228) for filling in the trench region(214). At this time, trench region(214) further includes a deep trench region(214d) formed through the upper silicon layer(204) to the upper surface of the buried insulator layer(202), and a shallow trench region(214s) formed at the peripheral portion of the deep trench region(214d). The isolation structure(228) further comprises a trench oxide layer(216), a trench liner(218a) and an isolating layer pattern(224p) for filling in the trench region(214).
Abstract:
PURPOSE: A fine transistor and a method for manufacturing the same are provided to make a manufacturing process simple by forming a space through a round etching and forming a SONOS cell using a charge trap layer. CONSTITUTION: In a fine transistor and a method for manufacturing the same, a tunnel oxide film is formed on a semiconductor substrate(100). A nitride film and a passivation are formed on the tunnel oxide film(110), and the passivation is pattern and is used as a mask to etch the nitride film, and charge trapping layers(123) which are separated from each other. A blocking insulation film(124) is formed on a formed nitride film, and an electrode is formed on the blocking oxide film and the tunnel oxide film.
Abstract:
측정용 패턴을 개선하여 측정의 신뢰도를 향상시킬 수 있는 측정용 패턴을 구비하는 반도체장치 및 이를 이용한 반도체장치의 측정방법이 개시된다. 본 발명에 따른 측정용 패턴을 구비하는 반도체장치는, 반도체 집적회로가 형성되는 칩영역과 상기 칩영역을 둘러싸는 스크라이브영역을 포함하는 반도체기판; 상기 스크라이브영역 내의 상기 반도체기판의 표면에 빈 공간의 형태로 형성되며, 계측설비의 측정용 빔이 투사되는 빔영역이 포함될 수 있도록 일정한 표면 단면적을 갖는 측정용 패턴; 및 상기 측정용 패턴의 내부에, 상기 측정용 패턴의 빈 공간의 표면 단면적을 감소, 예를 들어 빔영역의 표면 단면적 대비 더미 패턴의 표면 단면적의 비율이 5% 내지 15%가 될 수 있도록 더미 패턴을 포함한다.
Abstract:
A split-gate type non-volatile memory device is provided to increase the voltage induced to a floating gate and improve a program characteristic by additionally forming the planarized second insulation layer on the first insulation layer. A semiconductor substrate(200) is prepared. A gate insulation layer pattern(230) is formed on the semiconductor substrate. A floating gate pattern(240) which is thinner in its center portion than both its edge portions is formed on the gate insulation layer pattern. An interpoly dielectric(270) is formed on the floating gate pattern, including the first and second insulation layers(250,260). The first insulation layer is thinner in both its edge portions than its center portion, The second insulation layer which is thicker in its center portion than both its edge portions to make the upper surface flat is formed on the first insulation layer. One sidewall of the resultant structure and the upper surface of the semiconductor substrate adjacent to the one sidewall are covered with a tunnel insulation layer pattern(290). A control gate pattern(300) is formed on the tunnel insulation layer pattern.
Abstract:
PURPOSE: A method for manufacturing a split gate type flash memory device is provided to be capable of forming a floating gate pattern without forming misalignment and approximity effect. CONSTITUTION: A trench isolation layer(58) is formed on a semiconductor substrate for defining a plurality of first active regions(62a) and a plurality of second active regions(62b). Floating gate patterns(64) spaced apart from each other are formed on the first active regions(62a) by etching a conductive pattern using an oxide pattern as a mask. A tunnel oxide layer is formed at both sidewalls of the floating gate patterns(64). A plurality of control gate electrodes are formed on the floating gate patterns.
Abstract:
PURPOSE: A method of manufacturing a semiconductor device having a borderless contact hole is provided to prevent a leakage current pass caused from the recess of a device isolation by over etch in the contact formation that exposes an impurity region and the nearest trench isolation layer at the same time. CONSTITUTION: A trench isolation layer formed on the first conductive type semiconductor substrate(101) is recessed to have a constant depth and the upper sidewall of an active region is exposed. By implanting the second impurity ion into the exposed upper sidewall, an impurity region(130) is formed on the surface of the active region and the exposed upper sidewall. An interlayer dielectric(109) is formed on the semiconductor substrate having the impurity region. By patterning the interlayer dielectric, a contact hole(110) that exposes simultaneously an impurity region and the nearest trench isolation layer is formed.
Abstract:
A method for manufacturing an embedded flash memory device is provided to enhance the reliability of the embedded flash memory device by preventing deterioration of logic conformity in a logic region. A first region and a second region are defined on a semiconductor substrate(110). A floating gate structure is formed to interpose a first gate insulating layer pattern(114a) into the first region. A second gate insulating layer(125) is formed on the semiconductor substrate of the first region and the second region including the floating gate structure. A well is formed within the semiconductor substrate of the second region including the second gate insulating layer. The first and the second region correspond to a flash memory cell region and a logic region. The logic region includes a low voltage region and a high voltage region. The second gate insulating layer of the high voltage region is thicker than a first gate insulating layer pattern.
Abstract:
A nonvolatile memory device and its manufacturing method are provided to reduce damage of the nonvolatile memory device due to ion implantation for forming a source region by minutely patterning a floating gate in a small size. A source region(260) is formed in a semiconductor substrate(100). A part of a gate dielectric is overlapped with the source region. A floating gate(220) is formed on an upper portion of the gate dielectric. Electric field of the floating gate is constantly formed on the region overlapped with the source region. A control gate(250) is formed to be insulated from an upper portion of the floating gate along a sidewall of the floating gate. An intergate dielectric is disposed between the floating gate and the control gate. A drain region(270) is formed in the proximity of the other side of the control gate. A side of the floating gate adjacent to the source region has a curvature smaller than the other side of the floating gate.
Abstract:
개선된 팁 프로파일과 균일한 두께의 게이트 절연막을 갖는 스플릿 게이트 타입의 불휘발성 메모리 장치의 제조 방법에서, 제1 게이트 절연막 및 제1 도전막이 기판 상에 형성되며, 산화막 패턴은 상기 도전막을 부분적으로 산화시킴으로써 형성된다. 상기 산화막 패턴을 마스크로 사용하여 상기 제1 도전막을 식각함으로써 상기 제1 게이트 절연막 상에 플로팅 게이트 전극이 형성된다. 상기 플로팅 게이트 전극이 형성된 기판의 전체 표면 상에 제1 실리콘막을 형성한 후, 상기 제1 실리콘막을 산화시킴으로써 상기 플로팅 게이트 전극의 측면들 및 상기 플로팅 게이트 전극과 인접하는 상기 기판의 표면 부위들 상에 터널 절연막 및 제2 게이트 절연막이 각각 형성된다. 상기 터널 절연막 및 상기 제2 게이트 절연막 상에 컨트롤 게이트 전극을 형성한다. 상기 컨트롤 게이트 전극이 형성된 기판의 전체 표면 상에 제2 실리콘막을 형성하고, 상기 제2 실리콘막을 열산화막으로 형성한다.
Abstract:
반도체 기판 내부에 산화층이 형성된 모스 트랜지스터의 형성 방법에 관해 개시한다. 게이트 산화막을 형성하기 위한 산화층을 반도체 기판 내에 형성하고, 그 상면의 반도체 기판을 직접 식각하여 주입 깊이와 동일한 높이의 게이트를 형성함으로써, 두께가 얇고 안정성이 좋은 게이트 산화막을 형성할 수 있다. 산화층, 이온 주입