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公开(公告)号：KR100413182B1
公开(公告)日：2003-12-31
申请号：KR1020010075186
申请日：2001-11-30
Applicant: 한국전자통신연구원
IPC: H03F3/45
CPC classification number: H03G1/007 , H03F3/45179 , H03F2203/45492 , H03G1/0023
Abstract: An automatically gain controllable linear differential amplifier using a variable degeneration resistor is disclosed. The linear differential amplifier includes an input end, a bias current source, a load unit, a first MOS transistor and a second MOS transistor. The linear differential amplifiers of the present invention can control an amplifying gain according to an input signal and improve linearity IIP3 without needing additional power consumption caused by improving the linearity The automatically gain controllable linear differential amplifier uses NMOS/PMOS transistor so an integration process of the amplifier can be implemented more conveniently and efficiently.
Abstract translation: 公开了一种使用可变负反馈电阻的自动增益可控的线性差分放大器。 线性差分放大器包括输入端，偏置电流源，负载单元，第一MOS晶体管和第二MOS晶体管。 本发明的线性差分放大器可以根据输入信号控制放大增益并且改善线性度IIP3，而不需要由增加线性度引起的额外功耗。自动增益可控的线性差分放大器使用NMOS / PMOS晶体管， 放大器可以更加方便和高效地实现。
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公开(公告)号：KR1020030044444A
公开(公告)日：2003-06-09
申请号：KR1020010075186
申请日：2001-11-30
Applicant: 한국전자통신연구원
IPC: H03F3/45
CPC classification number: H03G1/007 , H03F3/45179 , H03F2203/45492 , H03G1/0023
Abstract: PURPOSE: A differential linear amplifier is provided to improve the linearity(IIP3) viewed from the input side by controlling the gain of the amplification in response to the input signal applied to the differential amplifier as well as improve the IIP3 by utilizing a poly silicon without using the polysilicon as a resistor, thereby obtaining an excellent characteristics. CONSTITUTION: A differential linear amplifier includes an input block for receiving a positive input signal and a negative input signal, a bias current source provided on one side of the input block for supplying a bias current, a pair of load blocks(110,120) provided on the other side of the input block for supplying the different level between the output signals between the positive output terminal and the negative output terminal corresponding to the positive input signal and the negative input signal, a first MOD transistor(210) connected between the bias current source and the input block for utilizing the positive input signal as a gate input and the gain control signal as a substrate bias voltage and a second MOS transistor(220) connected between the bias current source and the input block for utilizing the negative input signal as a gate input and the gain control signal as a substrate bias voltage.
Abstract translation: 目的：提供差分线性放大器，以通过控制放大器的输入信号来响应于差分放大器的输入信号来控制从输入侧观察的线性度（IIP3），并通过利用多晶硅来改善IIP3，而不需要 使用多晶硅作为电阻器，从而获得优异的特性。 构成：差分线性放大器包括用于接收正输入信号和负输入信号的输入块，设置在用于提供偏置电流的输入块的一侧上的偏置电流源，设置在该输入块上的一对加载块（110,120） 用于在与正输入信号和负输入信号相对应的正输出端和负输出端之间的输出信号之间提供不同电平的输入块的另一侧;连接在偏置电流之间的第一MOD晶体管（210） 源极和用于利用正输入信号作为栅极输入和增益控制信号作为衬底偏置电压的输入块和连接在偏置电流源和输入块之间的第二MOS晶体管（220），以将负输入信号用作 栅极输入和增益控制信号作为衬底偏置电压。
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公开(公告)号：KR1020030013191A
公开(公告)日：2003-02-14
申请号：KR1020010047547
申请日：2001-08-07
Applicant: 한국전자통신연구원
IPC: H01F27/25
Abstract: PURPOSE: An integrated inductor is provided to reduce a substrate loss according to a magnetic field which directs to a substrate and restrain a generation of a counter electromotive force due to an interference between adjacent metal lines. CONSTITUTION: A metal line includes the first spiral line(21) and the second spiral line(22). The second spiral line(22) is connected to the first spiral line(21) through a contact point(21a). The first spiral line(21) and the second spiral line(22) are arranged in various shapes such as a square, a circle, and a hexagon. The metal line uses a metal film which is laminated by a single layer or a multiple layer. A protective film(32) is formed on the metal line. The first interlayer dielectric(31) is formed on a silicon substrate(30). A metal film is deposited on the first interlayer dielectric(31), and is selectively etched to form the metal line having the first and second spiral lines(21,22).
Abstract translation: 目的：提供集成电感器，以根据指向衬底的磁场减少衬底损耗，并抑制由于相邻金属线之间的干扰而产生反电动势。 构成：金属线包括第一螺旋线（21）和第二螺旋线（22）。 第二螺旋线（22）通过接触点（21a）连接到第一螺旋线（21）。 第一螺旋线（21）和第二螺旋线（22）被布置成各种形状，例如正方形，圆形和六边形。 金属线使用通过单层或多层层压的金属膜。 在金属线上形成保护膜（32）。 第一层间电介质（31）形成在硅衬底（30）上。 金属膜沉积在第一层间电介质（31）上，并被选择性地蚀刻以形成具有第一和第二螺旋线（21,22）的金属线。
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公开(公告)号：KR1020130029327A
公开(公告)日：2013-03-22
申请号：KR1020120052200
申请日：2012-05-16
Applicant: 한국전자통신연구원
Abstract: PURPOSE: A single frequency synthesizer based FDD(Frequency Division Duplex) transceiver is provided to execute frequency upper and lower conversion by using a single frequency synthesizer. CONSTITUTION: A duplexer(630) transmits a signal of an RF(Radio Frequency) band through an antenna. A receiver(650) amplifies the received RF band signal from the antenna through the duplexer. The receiver executes the lower frequency conversion of the amplified signal. The receiver processes the analog signal processing of the lower frequency converted signal. A frequency synthesizer(660) generates a carrier frequency for executing the frequency lower conversion in the receiver by executing an upper frequency conversion in a transmitter. [Reference numerals] (610) Transmission signal processing unit; (611) Digital filter; (612) IF up-conversion unit; (613) IF generating and processing unit; (622) Analog front-end unit; (623) RF up-conversion unit; (624) Bandpass filter; (630) Duplexer; (650) Receiver; (660) Frequency synthesizer; (AA) Digital baseband 1; (BB) Digital baseband Q; (CC) Transmission frequency information; (DD) Reception frequency information
Abstract translation: 目的：提供基于单频合成器的FDD（频分双工）收发器，通过使用单个频率合成器来执行频率上下转换。 构成：双工器（630）通过天线发送RF（射频）频带的信号。 接收机（650）通过双工器放大从天线接收的RF频带信号。 接收机执行放大信号的较低频率转换。 接收器处理较低频率转换信号的模拟信号处理。 频率合成器（660）通过在发射机中执行较高的频率转换来产生用于在接收机中执行频率较低转换的载波频率。 （附图标记）（610）发送信号处理单元; （611）数字滤波器; （612）IF上变频单元; （613）IF生成处理单元; （622）模拟前端单元; （623）RF上变频单元; （624）带通滤波器; （630）双工器; （650）接收器; （660）频率合成器; （AA）数字基带1; （BB）数字基带Q; （CC）传输频率信息; （DD）接收频率信息
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公开(公告)号：KR1020110092197A
公开(公告)日：2011-08-17
申请号：KR1020100098106
申请日：2010-10-08
Applicant: 한국전자통신연구원
Inventor： 한선호
IPC: H04B1/10
CPC classification number: H04B1/30
Abstract: PURPOSE: A sub-sampling based receiver using a frequency selective noise canceller is provided to improve the performance of a digital receiver. CONSTITUTION: An FSSD(Frequency Selective Single to Differential converter)(32) has a band pass filter function. The FSSD changes a single input signal into a differential signal in a desired signal penetration frequency band. The FSSD changes the single input signal into a common mode signal in a not-desired signal frequency band. A CMR(Common Mode Rejector)(34) is operated as a load with a certain impedance about the differential signal which is outputted from the FSSD. The CMR functions as a filter for all common mode signals.
Abstract translation: 目的：提供使用频率选择性噪声消除器的基于子采样的接收机，以提高数字接收机的性能。 构成：FSSD（频率选择性单差分转换器）（32）具有带通滤波器功能。 FSSD将单个输入信号改变成期望的信号穿透频带中的差分信号。 FSSD将单个输入信号改变为不期望的信号频带中的共模信号。 CMR（共模抑制器）（34）作为从FSSD输出的差分信号的一定阻抗工作。 CMR作为所有共模信号的滤波器。
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Patent Agency Ranking
公开(公告)号：KR1020110070719A
公开(公告)日：2011-06-24
申请号：KR1020100038681
申请日：2010-04-26
Applicant: 한국전자통신연구원
CPC classification number: H03L7/1806 , G04F10/005 , H03L7/095 , H03L7/0991 , H03L2207/50 , H03M1/1205
Abstract: PURPOSE: A time to digital converter(TDC) and a complete digital phase locked loop including the same are provided to detect minute phase error required in compensating phase difference between a DCO clock and a reference clock, by installing the TDC. CONSTITUTION: A complete digital PLL(100) accumulates a frequency setting word value and a phase of a DCO clock. A phase counter(200) detects minute phase difference between a reference clock and a rising edge re-timed clock. A phase detector(300) compensates phase difference between a FSW(Frequency setting word) and the DCO clock. The phase detector detects a digital phase error value. A digital loop filter(400) controls PLL loop operation characteristics by filtering the digital phase error value. A lock detector(500) generates a lock indication signal. A digital controlled oscillator(600) controls the frequency of the DCO clock according to the output of the digital loop filter. A re-timed clock generator(700) outputs re-timed clocks.
Abstract translation: 目的：通过安装TDC，提供数字转换器（TDC）和包含该数字转换器（TDC）的完整数字锁相环，以检测补偿DCO时钟和参考时钟之间的相位差所需的微小相位误差。 构成：完整的数字PLL（100）累加频率设定字值和DCO时钟的相位。 相位计数器（200）检测参考时钟和上升沿重新定时时钟之间的微小相位差。 相位检测器（300）补偿FSW（频率设定字）与DCO时钟之间的相位差。 相位检测器检测数字相位误差值。 数字环路滤波器（400）通过滤波数字相位误差值来控制PLL环路操作特性。 锁定检测器（500）产生锁定指示信号。 数字控制振荡器（600）根据数字环路滤波器的输出控制DCO时钟的频率。 重新定时的时钟发生器（700）输出重新定时的时钟。
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公开(公告)号：KR100988460B1
公开(公告)日：2010-10-20
申请号：KR1020080087904
申请日：2008-09-05
Applicant: 한국전자통신연구원
CPC classification number: H03F1/26 , H03F1/565 , H03F3/195 , H03F2200/222 , H03F2200/294 , H03F2200/36 , H03F2200/451
Abstract: 본 발명은 광대역 저잡음 증폭기에 관한 것으로, 입력 신호를 증폭하여 상기 입력 신호와 반대되는 위상을 가지는 제1신호를 출력하는 소스-디제너레이티드 공통 소스 증폭기; 상기 소스-디제너레이티드 공통 소스 증폭기에 병렬 연결되어, 상기 입력 신호를 증폭하여 상기 입력 신호와 동일한 위상을 가지는 제2신호를 출력하는 공통 게이트 증폭기; 및 상기 소스-디제너레이티드 공통 소스 증폭기와 상기 공통 게이트 증폭기의 입력단을 격리시키며 정합 주파수 대역을 결정하는 정합 주파수 대역 결정부를 포함하여 구성되며, 이에 의하여 안정적인 광대역 정합 특성을 제공하면서도 높은 전력 이득 및 낮은 잡음 특성을 제공할 수 있도록 한다. 또한, 단일 신호를 차동 신호로 자체 변환할 수 있도록 하여, 우수한 단일 종단-차동 특성을 제공함과 동시에 설계 또한 간단해지도록 해준다.
광대역 저잡음 증폭기, 광대역 정합 특성, 높은 전력 이득,-
公开(公告)号：KR1020100028938A
公开(公告)日：2010-03-15
申请号：KR1020080087904
申请日：2008-09-05
Applicant: 한국전자통신연구원
CPC classification number: H03F1/26 , H03F1/565 , H03F3/195 , H03F2200/222 , H03F2200/294 , H03F2200/36 , H03F2200/451
Abstract: PURPOSE: A broadband low noise amplifier is provided to obtain high single end-differential property by changing a single signal into a differential signal. CONSTITUTION: A source-degenerated common source amplifier is provided to output a first signal with an opposite phase to an input signal by amplifying the input signal. A common gate amplifier is connected in parallel to the source-degenerated common source amplifier. The common gate amplifier outputs a second signal with the same phase as the input signal by amplifying the input signal. A matching frequency band determining unit separates an input terminal of the common gate amplifier and the source-degenerated common source amplifier. The matching frequency band determining unit is comprised of the first impedance(13) and the second impedance(14).
Abstract translation: 目的：提供宽带低噪声放大器，通过将单个信号变为差分信号来获得高单端差分特性。 构成：提供源极退化的公共源放大器，通过放大输入信号来输出具有与输入信号相反的相位的第一信号。 公共栅极放大器与源极退化的公共源放大器并联连接。 公共门放大器通过放大输入信号输出与输入信号相同相位的第二信号。 匹配频带确定单元分离公共栅极放大器和源极退化的共源放大器的输入端。 匹配频带确定单元包括第一阻抗（13）和第二阻抗（14）。
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公开(公告)号：KR100821126B1
公开(公告)日：2008-04-11
申请号：KR1020060072412
申请日：2006-07-31
Applicant: 한국전자통신연구원
IPC: H01G5/00
CPC classification number: H03B5/1243 , H03B5/1293
Abstract: 본 발명은 제어전압의 변화에 대해서 선형적인 주파수 가변 특성을 가지고, 이를 통해 전체 제어전압에 대해서 일정한 이득을 얻을 수 있어 넓은 주파수 가변 범위를 얻을 수 있도록 제공하는 가변 캐패시터 회로를 구비한 장치를 제공하기 위한 것으로, 이를 위해 본 발명은 서로 병렬접속되어 구성되고, 입력되는 제어전압에 대해 서로 다른 캐패시턴스를 갖는 복수의 가변 캐패시터를 포함하며, 상기 제어전압의 전체 범위 내에서 가변하는 상기 제어전압의 동일 전압 레벨에 대한 상기 복수의 가변 캐패시터의 가변 캐패시턴스의 총합은 선형성을 갖는 가변 캐패시터 회로를 구비한 장치를 제공한다.
VCO(Voltage Controlled Oscillator), PLL(Phase Locked Loop), 가변 캐패시터, 바랙터(Varactor), 병렬 접속, 가변 캐패시터, 선형성, 주파수, 이득-
公开(公告)号：KR1020060070796A
公开(公告)日：2006-06-26
申请号：KR1020040109407
申请日：2004-12-21
Applicant: 한국전자통신연구원
IPC: H03F1/26
CPC classification number: H03F3/193 , H03F1/223 , H03F1/26 , H03F1/42 , H03F1/56 , H03F2200/168 , H03F2200/36 , H03F2200/372 , H03F2200/489
Abstract: 본 발명은 공통 소스(Common source) 및 소스 디제너제이션(Source degeneration) 구조를 가지면서, 최적화된 성능으로 넓은 가변 정합 주파수 대역을 가질 수 있는 저잡음 증폭기를 제공하기 위한 것으로, 이를 위해 본 발명은 전술한 과제를 달성하기 위해 공통 소스 및 소스 디제너제이션 구조를 가지는 저잡음 증폭기에 있어서, 신호를 입력받는 입력단에 일측이 연결된 제1 인덕터; 접지전압 공급단에 일측이 접속된 제2 인덕터; 상기 제1 인덕터에 게이트가 접속되고, 상기 제2 인덕터의 타측에 소스가 접속되며, 타측으로 신호를 전달하는 모스트랜지스터; 및 상기 입력단에서의 입력임피던스를 가변하기 위해 상기 모스트랜지스터의 소스와 게이트 사이에 구비된 가변 캐패시터를 구비하는 저잡음 증폭기를 제공한다.
통신, 저잡음 증폭기, 입력 정합, 임피던스.Abstract translation: 本发明提供一种低噪声放大器，其具有公共源极和源极负反馈结构，并且具有性能优化的宽可变匹配频带，为此， 1。一种低噪声放大器，具有用于实现问题的共用源极和源极简并结构，包括：第一电感器，其一端连接到用于接收信号的输入端子; 第二电感器，其一端连接到地电压供应端子; MOS晶体管，具有连接到所述第一电感器的栅极，连接到所述第二电感器的另一侧的源极和传输到另一侧的信号; 并且在MOS晶体管的源极和栅极之间提供可变电容器，用于改变输入端子处的输入阻抗。
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