公开(公告)号：DE2861136D1

公开(公告)日：1981-12-17

申请号：DE2861136

申请日：1978-09-06

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/70 ,  H01L23/48

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

公开(公告)号：AU3844878A

公开(公告)日：1980-01-31

申请号：AU3844878

申请日：1978-07-28

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/225 ,  H01L21/331 ,  H01L21/762 ,  H01L23/532 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/82 ,  H01L27/04 ,  H01L29/72 ,  H01L21/20 ,  H01L21/22 ,  H01L21/265 ,  H01L21/285 ,  H01L21/306 ,  H01L21/31

Abstract: A method for manufacturing a high performance bipolar device and the resulting structure which has a very small emitter-base spacing is described. The small emitter-base spacing, reduces the base resistance compared to earlier device spacing and thereby improves the performance of the bipolar device. The method involves providing a silicon semiconductor body having regions of monocrystalline silicon isolated from one another by isolation regions and a buried subcollector therein. A base region is formed in the isolated monocrystalline silicon. A mask is formed on the surface of the silicon body covering those regions designated to be the emitter and collector reach-through regions. A doped polycrystalline silicon layer is then formed through the mask covering the base region and making ohmic contact thereto. An insulating layer is formed over the polysilicon layer. The mask is removed from those regions designated to be the emitter and collector reach-through regions. The emitter junction is then formed in the base region and the collector reach-through formed to contact the buried subcollector. Electrical contacts are made to the emitter and collector. The doped polycrystalline silicon layer is the electrical contact to the base regions.

公开(公告)号：DE69208415T2

公开(公告)日：1996-09-19

申请号：DE69208415

申请日：1992-09-11

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  INTERRANTE MARIO JOHN ,  KADAKIA SURESH DAMONDARDAS ,  STOLLER HERBERT IVAN ,  MALAVIYA SHASHI DHAR ,  MCLEOD MARK HARRISON ,  RAY SUDIPTA KUMAR

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

公开(公告)号：DE3379699D1

公开(公告)日：1989-05-24

申请号：DE3379699

申请日：1983-07-13

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  BHATIA SATYAPAL SINGH ,  RISEMAN JACOB ,  VALSAMAKIS EMMANUEL A

IPC: H01L29/73 ,  H01L21/225 ,  H01L21/285 ,  H01L21/331 ,  H01L23/485 ,  H01L29/735 ,  H01L21/60 ,  H01L23/48

Abstract: The method and resulting structure for making contact to a narrow width PN junction region in any desired semiconductor body utilizes a substantially vertical conformal conductive layer (26) formed over the desired PN junction region (30, 32). The body is heated to a suitable temperature to cause a dopant to diffuse from the vertical conductive layer (26) into the semiconductor body to form the narrow width PN junction region (30, 32). A substantially horizontal conductive layer (22) makes contact to the substantially vertical layer (26) so as to have the horizontal conductive layer (22) in electrical contact to the PN junction region (30, 32). Electrical contacts (34, 36) can be established to the horizontal conductive layer at any convenient location. A lateral PNP transistor is one type of device that can be made.

公开(公告)号：DE3162991D1

公开(公告)日：1984-05-10

申请号：DE3162991

申请日：1981-10-29

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  LECHATON JOHN S ,  WALSH JAMES LEO

IPC: C01B33/12 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/312 ,  H01L21/76 ,  H01L21/31

公开(公告)号：DE2861117D1

公开(公告)日：1981-12-10

申请号：DE2861117

申请日：1978-10-03

Applicant: IBM

Inventor： ANANTHA NARASIPUR GUNDAPPA ,  BHATIA HARSARAN SINGH ,  WALSH JAMES LEO

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/07 ,  H01L27/082 ,  H01L29/06 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L27/08 ,  H01L21/70

公开(公告)号：DE69208415D1

公开(公告)日：1996-03-28

申请号：DE69208415

申请日：1992-09-11

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  INTERRANTE MARIO JOHN ,  KADAKIA SURESH DAMONDARDAS ,  STOLLER HERBERT IVAN ,  MALAVIYA SHASHI DHAR ,  MCLEOD MARK HARRISON ,  RAY SUDIPTA KUMAR

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/538 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40

Abstract: A direct distribution wiring system is provided which facilitates the effecting of repair or engineering change in a Multi-chip module (MCM) while eliminating the need for redistribution and/or buried connections between IC attachment pads and engineering change pads, thus eliminating the need for patterned conductor layers corresponding to such functions. The operation of the MCM is improved by the wiring system allowing the reduction of lumped capacitances by disconnection of defective conductors, accomplished by providing severable connectors in a direct distribution structure, as well as the elimination of redistribution wiring layers and increased IC density on the MCM. Full potential fault coverage as well as full discretion in reversible engineering changes is provided by forming all elements of the wiring system on the surface of the device.

公开(公告)号：DE3787429T2

公开(公告)日：1994-04-21

申请号：DE3787429

申请日：1987-05-19

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  ECKER MARIO ENRIQUE ,  JONES HARRY JORDAN ,  MALAVIYA SHASHI DHAR

IPC: H01L21/82 ,  G06F1/22 ,  H01L21/822 ,  H01L23/538 ,  H01L27/04 ,  H01L23/52 ,  G06F1/00

公开(公告)号：DE3783672D1

公开(公告)日：1993-03-04

申请号：DE3783672

申请日：1987-05-12

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  JONES HARRY JORDAN ,  MALAVIYA SHASHI DHAR

IPC: H03K19/082 ,  H03K19/086 ,  H03K19/173 ,  H02H3/38 ,  G05F1/20

Abstract: A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs (46,48), while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors (12,22), the collector dotting of their respective reference transistors (55,56), the emitter dotting of one input transistor (12) and a reference transistor (55) to a constant current source (90), the emitter dotting of the other input transistor (22) and the other reference transistor (56) to a different constant current source (100), and an inhibit circuit (72) for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.

公开(公告)号：DE3380431D1

公开(公告)日：1989-09-21

申请号：DE3380431

申请日：1983-02-23

Applicant: IBM

Inventor： BHATIA HARSARAN SINGH ,  DORLER JACK ARTHUR ,  GAUR SANTOSH PRASAD ,  LECHATON JOHN S ,  MOSLEY JOSEPH MICHAEL ,  SRINIVASAN GURUMAKONDA R

IPC: H01L29/73 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/04 ,  H01L27/082 ,  H01L29/10 ,  H01L21/82 ,  H01L27/06

Abstract: A process is described which permits the fabrication of very narrow base width bipolar transistors in selected areas of an integrated circuit chip and bipolar transistors of wider base width on other selected areas of the same integrated circuit chip. The ability to selectively vary the transistor characteristics from one region of an integrated circuit chip to another provides a valuable degree of freedom for design of integrated circuits. The bipolar transistors on an integrated circuit chip are processed up to the point of emitter formation using conventional techniques. But, prior to the emitter (34, 35) formation, the base area (22) which is to be the emitter (34) of the selected region havingthe very narrow base transistors is dry etched using reactive ion etching. The existing silicon nitride/silicon dioxide layers with the emitter opening therein are used as the etching mask for this reactive ion etching procedure. Once the etching is completed to the desired depth, the normal processing is resumed to form the emitters (34, 35) and rest of the metallization.